Hi Spencer, >> I've been told by both Bruno at Raisonance and our ST FAE that care needs to >> be taken with the stack pointer on STM8 processors. Apparently the bits 9 >> and 10 of the SP are fixed at one, so the range of the SP is really 0x600 - >> 0x7FF. > > I have so far worked on the basis that the following text in the STM8 > programmer's reference was true: "The 16-bit Stack Pointer provides > access to a 64K-level Stack.". However I now see that this is > qualified elsewhere as follows: "Depending on the product, the most > significant bits can be forced to a preset value."
I've been looking through the datasheets for various STM8 parts and see that generally the memory maps mention a particular stack size (512 bytes in the case of the STM8S105), but there is nothing that states that the device force some upper bits to particular values, leaving you with impression that it could just be a suggestion on how to allocate your memory. Nevertheless, there is the text in the programmer's reference "Depending on the product, the most significant bits can be forced to a preset value", and I found the following in an errata document: "Stack pointer address compatibility across STM8S105xx family devices is not currently possible due to the present RAM mapping.". So it looks a bit like the limitation was not highlighted to those generating the part-specific documentation. I was surprised that this has not caused me issues before, however, given that I have run several threads simultaneously with stack locations other than that described in the memory map. I decided to experiment with an STM8S105 device and this particular device seems to be happy to use a stack pointer outside of the 512 byte range. According to the memory map, this device should use stack in 0x600-0x7FF, however I can set the SP register to 0x3FF and on reading it back it still contains 0x3FF (implying that the bits are not fixed within the register). Furthermore if I carry out PUSH or POP instructions and examine the memory contents, they do indeed modify the memory below 0x3FF rather than modifying the 0x600-0x7FF range as you might expect. Either the limitation is part-specific or it only applies to particular addressing modes. I will seek clarification from ST about this. Best regards, Kelvin.
