In regards to the second question I asked in my previous email, I have
solved the issue of being able to read the software registers and snapshot
blocks. I needed to write the correct values to the software registers
after programming in order to properly initialize the design.
Thanks,
Mark
On Wed, Jun 28, 2017 at 12:33 PM, Peryer, Mark A. <
mark.per...@cfa.harvard.edu> wrote:
> Hello,
>
> There still appears to be an issue with the firmware version loaded onto
> the Virtex 7. As the image below shows, after a power cycle the SKARAB
> boots from the "multi-boot" image. However, once the .fpg file is uploaded,
> the Virtex 7 reverts back to using the toolflow image.
>
> Additionally, I have been having an issue reading the correct values
> stored in software registers and snapshot blocks in my JASPER design. Could
> this be related to booting from the incorrect firmware image, or is it a
> separate issue?
>
>
> [image: Inline image 1]
>
> Thanks,
>
> Mark
>
> On Tue, Jun 27, 2017 at 11:04 AM, Clifford van Dyk <
> cliffordvan...@gmail.com> wrote:
>
>> Excellent! Welcome to Skarab!
>>
>> Kind regards,
>> Clifford
>>
>> On 6/27/2017 3:55 PM, Young, Andre wrote:
>> > Hi Clifford, Adam
>> >
>> > Looks like it was the server NIC MTU size, I changed it from 1500 to
>> > 9000 and then:
>> >
>> > # skarab-01
>> > In [8]:
>> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-
>> 22_0944.fpg')
>> > Out[8]: True
>> >
>> > # skarab-02
>> > In [10]:
>> > fpga.upload_to_ram_and_program('realtimeaphids_6_20_2017-6-
>> 22_0944.fpg')
>> > Out[10]: True
>> >
>> > Issue with golden image boot noted, we'll continue to look at that.
>> >
>> > Thanks very much,
>> > André
>> >
>>
>>
>
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