On Mon, 07 Nov 2016, Lucas Nussbaum wrote: > On 06/11/16 at 17:41 -0200, Henrique de Moraes Holschuh wrote: > > On Sun, 06 Nov 2016, Ben Hutchings wrote: > > > It's worth noting that TSX is broken in 'Haswell' processors and is > > > supposed to be disabled via a microcode update. I don't know whether > > > glibc avoids using it on these processors if the microcode update is > > > not applied. (Linux doesn't appear to hide the feature flags.) > > > > It does avoid it. For glibc libpthreads, Debian has blacklisted Intel > > TSX use [in libpthreads] on all of Haswell and much of Broadwell. > > > > But anything else *will* attempt to use it, people query cpuid directly > > for these things. You need a hypervisor that filters cpuid(). > > How can one know what glibc does on a given CPU? (preferably without > access to the hardware) > > I could try to run an archive rebuild on hardware where glibc leverages > TSX to see what happens.
IMHO it would be better to instrument the locks in glibc with asserts, instead. You could use anything to test for pthread API violations, then. That said, if you are going to test Intel TSX for real, you need a Desktop Skylake-based Core i5/i7 or Xeon E3v5 that reports "RTM" in /proc/cpuinfo. Some won't. Not every Skylake model will have it enabled in the first place, and apparently the firmware can (and some _do_) disable it, especially on the mobile side. Please ensure the Skylake firmware has microcode 0x9d/0x9e or later, or install the latest version of the non-free intel-microcode package. The risk of unpredictable behaviour is quite real otherwise, and could mess up the test results (and corrupt data). Skylake errata are a nightmare. Note the AVX, AVX2, eDRAM (L4?), and TSX ones, as well as the power-management ones: http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e3-1200v5-spec-update.pdf http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/desktop-6th-gen-core-family-spec-update.pdf Don't attempt to test TSX with perf or intel PT running. perf is likely to cause too many aborts, and Intel PT is an errata hell. As for Broadwell, I don't know which processors would still have TSX enabled in the first place when running the latest microcode, and we blacklist most of them in glibc anyway (because almost all Broadwell-* specification updates list it as either unavailable or unusable), so they're not a very viable option to test this. -- Henrique Holschuh
