Mark Morgan Lloyd wrote on Mon, 01 Feb 2016:
For a demo computer built using this sort of thing, it's obviously
trivial to arrange it such that the simulator can load microcode
from persistent storage, and can do something comparable for a boot
loader.
What would be the comparable facility for the pipelined variant?
Loading lookup tables to decode opcodes to VLIW, and then clocking
those words through the pipeline?
You could use something FPGA-like to restructure your pipeline, but in
practice I indeed think many current architectures simply combine
microprogramming and pipelining, whereby the microprogramming
translates the externally visible ISA into an internal ISA (VLIW or
not), which in turn is executed in a pipelined fashion.
Jonas
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