Jonas Maebe wrote:
Mark Morgan Lloyd wrote on Mon, 01 Feb 2016:
For a demo computer built using this sort of thing, it's obviously
trivial to arrange it such that the simulator can load microcode from
persistent storage, and can do something comparable for a boot loader.
What would be the comparable facility for the pipelined variant?
Loading lookup tables to decode opcodes to VLIW, and then clocking
those words through the pipeline?
You could use something FPGA-like to restructure your pipeline, but in
practice I indeed think many current architectures simply combine
microprogramming and pipelining, whereby the microprogramming translates
the externally visible ISA into an internal ISA (VLIW or not), which in
turn is executed in a pipelined fashion.
Thanks for that. I'm still very much embroiled in porting a B5500
simulator, I've got it nicely split up into multiple threads (one per
CPU and IOP) which is something that the original author had a lot of
difficulty with but am stuck on some obscure opcode failure and will
have to bite the bullet and ask him for help.
Having got that coded and (hopefully) working, it would be interesting
to look at how much of the overall framework and peripherals could be
used for other large-scale computer systems- the sort of things that
SIMH isn't really a good fit for. I'm rather thinking of Stanford/SLAC
here, who went through an interesting progression of Burroughs and IBM
kit in the years before Hennessy did his RISC work there: and that of
course is where Wirth laid the foundations of Pascal.
But I sincerely hope I'm never bored enough to get too deeply into that :-)
--
Mark Morgan Lloyd
markMLl .AT. telemetry.co .DOT. uk
[Opinions above are the author's, not those of his employers or colleagues]
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