On Wed, 29 Nov 2006 13:25:18 -0500 Mark Lord <[EMAIL PROTECTED]> wrote:
> I'm betting that the ata_piix hardware has some kind of internal pipeline that > gets confused *sometimes* when a non-512 multiple passes through. Rarely, > though. It will do this if the FIFO setup is misconfigured. > I wonder if there's something on that device that we could bit-bang to reset > it's internal pipelines? That would cripple performance and just ask for more bizarre bugs. Firstly I think it makes sense to verify/play with the fifo and prefetch setup then verify the problem case and see what Intel think. Alan - To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html
