Re: L4re RAM/Flash usage and scheduling timing Info

2025-03-28 Thread Adam Lackorzynski
Hi Eric,

On Tue Mar 25, 2025 at 18:03:21 +, Eric Miniere wrote:
> Hello Adam,
> 
> Thank you for your interesting inputs.
> 
> I would like now to modify the given example supplied (GitHub - 
> kernkonzept/demo-l4re-micro-hypervisor: L4Re Micro Hypervisor demo for 
> Cortex-R52 and 
> Cortex-R82<https://github.com/kernkonzept/demo-l4re-micro-hypervisor>) that 
> run on Cortex R52, to adapt it to my board and add some "hello world" guests 
> at first.
> I did not find a doc/guide to change this example in particular.

Thanks for pointing this out. This repo is actually old and outdated,
we're in progress of retiring it.

> I followed the guide https://l4re.org/getting_started/make.html, but I did 
> not manage to cross compile with the tool chain 
> gcc-arm-none-eabi-10.3-2021.10. I hit errors when cross compiling L4re or 
> fiasco for FVP platform with armv8R (see attached log).
> 
> What would be your advice to avoid troubles at that stage ? I don't care to 
> use an old version, this is just for feasibility purpose.

Please use an arm-linux-gnueabihf-* toolchain instead of the
arm-none-eabi one. That should fix both issues. Further, the amount of
packages for the Cortex-R could be stripped down as, for example, the
AHCI block driver will not be of any use on a typical R52 platform. But
probably does not harm compiling it.



Adam

> 
> From: Adam Lackorzynski
> Sent: Saturday, March 22, 2025 12:42 AM
> To: Eric Miniere; [email protected]
> Cc: Nicola Bruno
> Subject: Re: L4re RAM/Flash usage and scheduling timing Info
> 
> [You don't often get email from [email protected]. Learn why this is important at 
> https://aka.ms/LearnAboutSenderIdentification ]
> 
> Hi,
> 
> On Tue Mar 18, 2025 at 10:11:54 +, Eric Miniere via l4-hackers wrote:
> > I am looking for an estimate of the memory footprint to run the hypervisor 
> > L4RE on a quad Core ARM Cortex R52.
> > Does it run directly from flash or it needs to be copied to run in RAM ? 
> > same question for Guests OS (ie FreeRtos)?
> 
> It can also run from flash. A guest as well I believe, but we never
> tried I think.
> 
> > What could be the minimal needed L4RE footprint for code and data ?
> 
> Depends on the config of course. Last time we checked, a config for
> 16VMs was around 400k. We're constantly trying to improve here.
> For the ratio between code/data I do not have numbers at hand but a good
> part is code that could/would be running off flash.
> 
> > Also if someone could share a rough idea of scheduling time for an ARM R52 
> > running at 400Mhz ? or nb of cycle it takes to schedule ?
> 
> On a Cortex-A53 (in-order) we're short over 2000 cycles in the
> measurements for a timer interrupt triggered switch, which would
> translate to 5µs at 400MHz. If VMs would be involved a little bit more
> because of the added state to swtich. I'd assume it would be in similar
> range on R52.
> 
> 
> Adam

> make[1]: Entering directory '/home/vboxuser/Hyp/L4re/l4re_projects/l4'
> make[3]: Nothing to be done for 'all'.
> make[3]: Nothing to be done for 'all'.
> make[4]: Nothing to be done for 'all'.
> === Building package "pkg/l4re-core/uclibc-headers" ===
> === Building package "pkg/l4re-core/libclang_rt-crt" ===
> make[3]: Nothing to be done for 'all'.
> === Building package "pkg/l4re-core/libgcc-crt" ===
> === Building package "pkg/l4re-core/compiler-rt-crt" ===
> make[2]: Nothing to be done for 'all'.
> === Building package "pkg/l4re-core/ldscripts" ===
> === Building package "pkg/l4re-core/libclang_rt-pure" ===
> make[3]: Nothing to be done for 'all'.
> === Building package "pkg/l4re-core/libgcc-pure" ===
> === Building package "pkg/l4re-core/libgcc_eh-headers" ===
> make[4]: Nothing to be done for 'all'.
> make[4]: Nothing to be done for 'all'.
> make[4]: Nothing to be done for 'all'.
> make[4]: Nothing to be done for 'all'.
> === Building package "pkg/l4re-core/libgcc_eh-pure" ===
> === Building package "pkg/l4re-core/libunwind_llvm-pure" ===
> make[3]: Nothing to be done for 'all'.
> === Building package "pkg/l4re-core/compiler-rt-pure" ===
> make[2]: Nothing to be done for 'all'.
> === Building package "pkg/l4re-core/libstdc++-headers" ===
>   [libstdc++-headers] ==> Updating symlinks 
> /home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/exception
>   [libstdc++-headers] ==> Updating symlinks 
> /h

Re: L4re RAM/Flash usage and scheduling timing Info

2025-03-28 Thread Eric Miniere via l4-hackers
Hello Adam,

Thank you for your interesting inputs.

I would like now to modify the given example supplied (GitHub - 
kernkonzept/demo-l4re-micro-hypervisor: L4Re Micro Hypervisor demo for 
Cortex-R52 and 
Cortex-R82<https://github.com/kernkonzept/demo-l4re-micro-hypervisor>) that run 
on Cortex R52, to adapt it to my board and add some "hello world" guests at 
first.
I did not find a doc/guide to change this example in particular.

I followed the guide https://l4re.org/getting_started/make.html, but I did not 
manage to cross compile with the tool chain gcc-arm-none-eabi-10.3-2021.10. I 
hit errors when cross compiling L4re or fiasco for FVP platform with armv8R 
(see attached log).

What would be your advice to avoid troubles at that stage ? I don't care to use 
an old version, this is just for feasibility purpose.

Thanks and Regards,

Eric Miniere


From: Adam Lackorzynski
Sent: Saturday, March 22, 2025 12:42 AM
To: Eric Miniere; [email protected]
Cc: Nicola Bruno
Subject: Re: L4re RAM/Flash usage and scheduling timing Info

[You don't often get email from [email protected]. Learn why this is important at 
https://aka.ms/LearnAboutSenderIdentification ]

Hi,

On Tue Mar 18, 2025 at 10:11:54 +, Eric Miniere via l4-hackers wrote:
> I am looking for an estimate of the memory footprint to run the hypervisor 
> L4RE on a quad Core ARM Cortex R52.
> Does it run directly from flash or it needs to be copied to run in RAM ? same 
> question for Guests OS (ie FreeRtos)?

It can also run from flash. A guest as well I believe, but we never
tried I think.

> What could be the minimal needed L4RE footprint for code and data ?

Depends on the config of course. Last time we checked, a config for
16VMs was around 400k. We're constantly trying to improve here.
For the ratio between code/data I do not have numbers at hand but a good
part is code that could/would be running off flash.

> Also if someone could share a rough idea of scheduling time for an ARM R52 
> running at 400Mhz ? or nb of cycle it takes to schedule ?

On a Cortex-A53 (in-order) we're short over 2000 cycles in the
measurements for a timer interrupt triggered switch, which would
translate to 5µs at 400MHz. If VMs would be involved a little bit more
because of the added state to swtich. I'd assume it would be in similar
range on R52.


Adam
make[1]: Entering directory '/home/vboxuser/Hyp/L4re/l4re_projects/l4'
make[3]: Nothing to be done for 'all'.
make[3]: Nothing to be done for 'all'.
make[4]: Nothing to be done for 'all'.
=== Building package "pkg/l4re-core/uclibc-headers" ===
=== Building package "pkg/l4re-core/libclang_rt-crt" ===
make[3]: Nothing to be done for 'all'.
=== Building package "pkg/l4re-core/libgcc-crt" ===
=== Building package "pkg/l4re-core/compiler-rt-crt" ===
make[2]: Nothing to be done for 'all'.
=== Building package "pkg/l4re-core/ldscripts" ===
=== Building package "pkg/l4re-core/libclang_rt-pure" ===
make[3]: Nothing to be done for 'all'.
=== Building package "pkg/l4re-core/libgcc-pure" ===
=== Building package "pkg/l4re-core/libgcc_eh-headers" ===
make[4]: Nothing to be done for 'all'.
make[4]: Nothing to be done for 'all'.
make[4]: Nothing to be done for 'all'.
make[4]: Nothing to be done for 'all'.
=== Building package "pkg/l4re-core/libgcc_eh-pure" ===
=== Building package "pkg/l4re-core/libunwind_llvm-pure" ===
make[3]: Nothing to be done for 'all'.
=== Building package "pkg/l4re-core/compiler-rt-pure" ===
make[2]: Nothing to be done for 'all'.
=== Building package "pkg/l4re-core/libstdc++-headers" ===
  [libstdc++-headers] ==> Updating symlinks 
/home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/exception
  [libstdc++-headers] ==> Updating symlinks 
/home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/new
  [libstdc++-headers] ==> Updating symlinks 
/home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/typeinfo
  [libstdc++-headers] ==> Updating symlinks 
/home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/cxxabi.h
  [libstdc++-headers] ==> Updating symlinks 
/home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/bits/exception_defines.h
  [libstdc++-headers] ==> Updating symlinks 
/home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/bits/cxxabi_forced.h
  [libstdc++-headers] ==> Updating symlinks 
/home/vboxuser/Hyp/L4re/l4re_projects/l4re_builds/armv8r/include/contrib/libstdc++-v3/cxxabi_forced.h
  [libstdc++-headers] ==> Updating symlinks

Re: L4re RAM/Flash usage and scheduling timing Info

2025-03-21 Thread Adam Lackorzynski
Hi,

On Tue Mar 18, 2025 at 10:11:54 +, Eric Miniere via l4-hackers wrote:
> I am looking for an estimate of the memory footprint to run the hypervisor 
> L4RE on a quad Core ARM Cortex R52.
> Does it run directly from flash or it needs to be copied to run in RAM ? same 
> question for Guests OS (ie FreeRtos)?

It can also run from flash. A guest as well I believe, but we never
tried I think.

> What could be the minimal needed L4RE footprint for code and data ?

Depends on the config of course. Last time we checked, a config for
16VMs was around 400k. We're constantly trying to improve here.
For the ratio between code/data I do not have numbers at hand but a good
part is code that could/would be running off flash.

> Also if someone could share a rough idea of scheduling time for an ARM R52 
> running at 400Mhz ? or nb of cycle it takes to schedule ?

On a Cortex-A53 (in-order) we're short over 2000 cycles in the
measurements for a timer interrupt triggered switch, which would
translate to 5µs at 400MHz. If VMs would be involved a little bit more
because of the added state to swtich. I'd assume it would be in similar
range on R52.


Adam
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