Enable the cryptographic engine available in the CP110 master on the
Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we
do not support multiple cryptographic engines yet.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/
for more advanced operations than the ones supported (as of now), but we
still need them to pass the data to the internal cryptographic engine.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/Kconfig | 17 +
drivers/crypto/Ma
/atenart/linux v4.11-rc1/7k8k-crypto
I can rebase if needed.
Thanks,
Antoine
Antoine Tenart (7):
Documentation/bindings: Document the SafeXel cryptographic engine
driver
crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
MAINTAINERS: add a maintainer for the Inside Secure
The Inside Secure Safexcel cryptographic engine is found on some Marvell
SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
.../bindings/crypto/inside-secure-safexcel.txt | 27 ++
1 file c
Enable the cryptographic engine available in the CP110 master on the
Armada 7040 DB.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/
The Safexcel EIP197 cryptographic engine is used on some Marvell SoCs,
such as Armada 7040 and Armada 8040. Enable this driver as a module in
the ARM64 defconfig.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 ins
Add the description of the crypto engine hardware block for the Marvell
Armada 7k and Armada 8k processors; for both the CP110 slave and master.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 15 +++
A new cryptographic engine driver was added in
drivers/crypto/inside-secure. Add myself as a maintainer for this
driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Hi Corentin,
On Fri, Apr 21, 2017 at 09:30:56AM +0200, Corentin Labbe wrote:
>
> I have some minor comment below
[…]
> > + /*
> > +* Result Descriptor Ring prepare
> > +*/
>
> This is not preferred comment format for one line
Sure.
>
> [...]
>
> > +static int
On Fri, Apr 21, 2017 at 01:36:45PM +0200, Corentin Labbe wrote:
> > > > + memset(ipad + keylen, 0, blocksize - keylen);
> > > > + memcpy(opad, ipad, blocksize);
> > > > +
> > > > + for (i = 0; i < blocksize; i++) {
> > > > + ipad[i] ^= 0x36;
> > > > +
Hi Thomas,
On Wed, Apr 12, 2017 at 10:56:08AM +0200, Thomas Petazzoni wrote:
> On Wed, 29 Mar 2017 14:44:29 +0200, Antoine Tenart wrote:
>
> > + cpm_crypto: crypto@80 {
> > + compatible = "inside
eye
> and I thought I'd give this a quick once-over to check for anything
> smelly. Unfortunately, I was not disappointed... ;)
:-)
> On 29/03/17 13:44, Antoine Tenart wrote:
> [...]
> > diff --git a/drivers/crypto/inside-secure/safexcel.c
> > b/drivers/crypto/inside
A new cryptographic engine driver was added in
drivers/crypto/inside-secure. Add myself as a maintainer for this
driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
functions to avoid double-freeing.
- Do not rely on sg_nents_for_len() to get the number of sg anymore.
- Added a dedicated kmalloc'ed cache to use for dma_map_single().
Antoine Tenart (3):
Documentation/bindings: Document the SafeXel cryptographic engine
driver
crypto: inside-secure: add
The Inside Secure Safexcel cryptographic engine is found on some Marvell
SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
.../bindings/crypto/inside-secure-safexcel.txt | 27 ++
1 file c
for more advanced operations than the ones supported (as of now), but we
still need them to pass the data to the internal cryptographic engine.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/Kconfig | 17 +
drivers/crypto/Ma
-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-secure/safexcel_hash.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/inside-secure/safexcel_hash.c
b/drivers/crypto/inside-secure/safexcel_hash.c
index 8527a5
com>
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-secure/safexcel_hash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/inside-secure/safexcel_hash.c
b/drivers/crypto/inside-secure/safexcel_hash.c
index
Hi,
On Mon, Jul 17, 2017 at 11:45:19AM +0200, Antoine Tenart wrote:
> The safexcel_hmac_sha1_setkey function checks if an invalidation command
> should be issued, i.e. when the context ipad/opad change. This checks is
> done after filling the ipad/opad which and it can't be true.
- add SafeXcel EIP197 crypto engine
driver")
Reported-by: Dan Carpenter <dan.carpen...@oracle.com>
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
Since v1: added the Fixes tag.
drivers/crypto/inside-secure/safexcel_hash.c | 2 +-
1 file changed, 1 insertion(+
: 1b44c5a60c13 ("crypto: inside-secure - add SafeXcel EIP197 crypto engine
driver")
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
Since v1: added the Fixes tag.
drivers/crypto/inside-secure/safexcel_hash.c | 6 +++---
1 file changed, 3 insertions(+), 3 de
DMA
API helper.
- Removed some DMA free functions to avoid double-freeing.
- Do not rely on sg_nents_for_len() to get the number of sg anymore.
- Added a dedicated kmalloc'ed cache to use for dma_map_single().
Antoine Tenart (3):
Documentation/bindings: Document the SafeXel cryptographic
The Inside Secure Safexcel cryptographic engine is found on some Marvell
SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
.../bindings/crypto/inside-secure-safexcel.txt | 27 ++
1 file c
for more advanced operations than the ones supported (as of now), but we
still need them to pass the data to the internal cryptographic engine.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/Kconfig | 17 +
drivers/crypto/Ma
A new cryptographic engine driver was added in
drivers/crypto/inside-secure. Add myself as a maintainer for this
driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
A new cryptographic engine driver was added in
drivers/crypto/inside-secure. Add myself as a maintainer for this
driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Hi Igal,
On Mon, Apr 24, 2017 at 08:50:32AM +, Igal Liberman wrote:
> [...]
>
> > + priv->clk = of_clk_get(dev->of_node, 0);
> > + if (!IS_ERR(priv->clk)) {
> > + ret = clk_prepare_enable(priv->clk);
> > + if (ret) {
> > + dev_err(dev, "unable to
for more advanced operations than the ones supported (as of now), but we
still need them to pass the data to the internal cryptographic engine.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/Kconfig | 17 +
drivers/crypto/Ma
The Inside Secure Safexcel cryptographic engine is found on some Marvell
SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
.../bindings/crypto/inside-secure-safexcel.txt | 27 ++
1 file c
cache to use for dma_map_single().
Antoine Tenart (3):
Documentation/bindings: Document the SafeXel cryptographic engine
driver
crypto: inside-secure: add SafeXcel EIP197 crypto engine driver
MAINTAINERS: add a maintainer for the Inside Secure crypto driver
.../bindings/crypto/inside
Hi Stephan,
On Mon, Apr 24, 2017 at 02:59:05PM +0200, Stephan Müller wrote:
> Am Montag, 24. April 2017, 09:54:06 CEST schrieb Antoine Tenart:
>
> > +struct safexcel_cipher_ctx {
> > + struct safexcel_context base;
> > + struct safexcel_crypto_priv *
Hi Robin,
On Wed, May 03, 2017 at 12:57:25PM +0100, Robin Murphy wrote:
> On 24/04/17 08:54, Antoine Tenart wrote:
> > +
> > +#include
>
> everywhere, please.
>
> Other than that, the DMA aspects all look much nicer now, thanks.
I'll update and resend a serie
On Tue, Jun 20, 2017 at 11:37:47AM +0800, Herbert Xu wrote:
> On Sun, Jun 11, 2017 at 10:53:53AM +0200, Antoine Tenart wrote:
> > On Wed, May 24, 2017 at 04:10:31PM +0200, Antoine Tenart wrote:
> > > The Inside Secure Safexcel cryptographic engine is found on some Marvell
The dma-mask property is broken and was removed in the device trees
having a safexcel-eip197 node and in the safexcel cryptographic
driver. This patch removes the dma-mask property from the documentation
as well.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
Documen
Remove the dma mask parsing from dt as this should not be encoded into
the engine device tree node. Keep the fallback value for now, which
should work for the boards already supported upstream.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
Hi Herbert,
As point
Hi Thomas,
On Mon, May 22, 2017 at 09:34:16PM +0200, Thomas Petazzoni wrote:
> On Mon, 22 May 2017 16:45:11 +0200, Antoine Tenart wrote:
> > + interrupts = > IRQ_TYPE_LEVEL_HIGH)>,
>
> You already got the feedback previously that an interrupt that is both
> ed
a dedicated kmalloc'ed cache to use for dma_map_single().
Antoine Tenart (5):
Documentation/bindings: Document the SafeXel cryptographic engine
driver
arm64: marvell: dts: fix interrupts in 7k/8k crypto nodes
arm64: marvell: dts: add dma-mask in crypto nodes for 7k/8k
crypto: inside-secure
for more advanced operations than the ones supported (as of now), but we
still need them to pass the data to the internal cryptographic engine.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/Kconfig | 17 +
drivers/crypto/Ma
The EIP197 cryptographic engine supports 64 bits address width but is
limited to 40 bits on 7k/8k. Add a dma-mask property in the
cryptographic engine nodes to reflect this.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-maste
A new cryptographic engine driver was added in
drivers/crypto/inside-secure. Add myself as a maintainer for this
driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
The Inside Secure Safexcel cryptographic engine is found on some Marvell
SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
.../bindings/crypto/inside-secure-safexcel.txt | 29 ++
1 file c
The cryptographic engine nodes have an interrupt which is configured as
both edge and level, which makes no sense at all. Fix this by
configuring it the right way (level).
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm64/boot/dts/marvell/armada-cp110-maste
for more advanced operations than the ones supported (as of now), but we
still need them to pass the data to the internal cryptographic engine.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/Kconfig | 17 +
drivers/crypto/Ma
The Inside Secure Safexcel cryptographic engine is found on some Marvell
SoCs (7k/8k). Document the bindings used by its driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
.../bindings/crypto/inside-secure-safexcel.txt | 29 ++
1 file c
On Mon, May 22, 2017 at 03:48:30PM +0100, Marc Zyngier wrote:
> On 22/05/17 15:30, Antoine Tenart wrote:
> > On Wed, May 03, 2017 at 05:36:38PM +0100, Marc Zyngier wrote:
> >> On 24/04/17 08:54, Antoine Tenart wrote:
> >>> +
> >>> + crypto: crypto@800
Hi Marc,
On Wed, May 03, 2017 at 05:36:38PM +0100, Marc Zyngier wrote:
> On 24/04/17 08:54, Antoine Tenart wrote:
> > +
> > + crypto: crypto@80 {
> > + compatible = "inside-secure,safexcel-eip197";
> > + reg = <0x8000
to dma_set_mask_and_coherent() before calling any DMA
API helper.
- Removed some DMA free functions to avoid double-freeing.
- Do not rely on sg_nents_for_len() to get the number of sg anymore.
- Added a dedicated kmalloc'ed cache to use for dma_map_single().
Antoine Tenart (4):
Documentation
A new cryptographic engine driver was added in
drivers/crypto/inside-secure. Add myself as a maintainer for this
driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
Hi Corentin,
On Mon, May 29, 2017 at 04:47:57PM +0200, Corentin Labbe wrote:
> On Wed, May 24, 2017 at 09:06:50PM +0200, Antoine Tenart wrote:
> > + .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
> > +CRYPTO_ALG_KERN_DRIVER_ONL
Do not use DMA is the request is 0 length.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
b/drivers/crypto/sunxi-ss/su
other users too.
Patch 12 adds a cryptographic engine node for sun5i SoCs.
Thanks,
Antoine
Since v1:
- Fixed a typo.
- Made the CRYPTO_ALG_KERN_DRIVER_ONLY flag addition in a dedicated
patch.
Antoine Tenart (12):
crypto: sun4i-ss: group variable definitions in sun4i_hash()
crypto
Update the sun4i-ss driver to use the skcipher API instead of the old
ablkcipher one. It's a bit more tricky than s/ablkcipher/skcipher/, but
still nothing special and the driver's logic stays the same.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/su
Cosmetic clean up if conditional checks on 0s values.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 28 +++---
drivers/crypto/sunxi-ss/sun4i-ss-core.c | 10
drivers/crypto/sunxi-ss/sun4i-ss-
reading the computed digest to ensure it is
available in the SS_MD[] registers.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/crypto/sunxi-ss/su
The CRYPTO_ALG_KERN_DRIVER_ONLY flag is set for hardware accelerated
ciphers accessible through a kernel driver only. This is the case for
ciphers exposed by the sun4i-ss driver. This patch sets this flag.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto
A bit is appended at the end of the input buffer for sha1. Simplify the
code assigning it.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/
Add a node for the cryptographic engine that can be found on sun5i SoCs.
This cryptographic engine is compatible with the Allwinner cryptographic
accelerator driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm/boot/dts/sun5i.dtsi | 8
1 file chan
Use the GENMASK helper instead of custom calculations to generate masks,
It also helps the readability.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
Cosmetic change to avoid having a full screen a variable definitions. It
also helps to see which variables share the same type.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 31 +++
1 file chang
Parts of the bf buffer were dynamically set to 0. Change this to set the
whole buffer to 0 by default to avoid any mistake.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Hi Corentin,
On Fri, May 26, 2017 at 04:55:01PM +0200, Corentin Labbe wrote:
> On Wed, May 24, 2017 at 09:06:51PM +0200, Antoine Tenart wrote:
> >
> > + /*
> > +* The datasheet isn't very clear about when to retrieve the digest. The
> > +* bit SS_DATA_END
Hi Maxime,
On Mon, May 29, 2017 at 10:29:31AM +0200, Maxime Ripard wrote:
> On Mon, May 29, 2017 at 10:09:44AM +0200, Antoine Tenart wrote:
> > > Which speed are the SS clocks ?
> >
> > The AHB SS clk is running at 300 MHz and the SS clk at 150 MHz. SS clk
> > is at
Hello,
On Sun, May 28, 2017 at 11:09:43AM +0530, PrasannaKumar Muralidharan wrote:
> On 24 May 2017 at 19:40, Antoine Tenart
> <antoine.ten...@free-electrons.com> wrote:
> > Add support for Inside Secure SafeXcel EIP197 cryptographic engine,
> > which can be found on
Hi Maxime,
On Tue, May 30, 2017 at 08:48:11AM +0200, Maxime Ripard wrote:
> On Mon, May 29, 2017 at 10:27:38PM +0200, Antoine Tenart wrote:
> > Add a node for the cryptographic engine that can be found on sun5i SoCs.
> > This cryptographic engine is compatible with the Allwinne
Hello Derek,
On Tue, May 30, 2017 at 06:09:37PM +1200, Derek Robson wrote:
> Fixed block comments across whole ccree driver
Since all these commits are doing the same logical change across a
single driver, you could probably squash them all into a single one.
Thanks!
Antoine
--
Antoine
Replace custom bit shifts and masks with lower/upper_32_bits helpers.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin Labbe <clabbe.montj...@gmail.com>
Acked-by: Corentin Labbe <clabbe.montj...@gmail.com>
---
drivers/crypto/sunxi-ss/su
A bit is appended at the end of the input buffer for sha1. Simplify the
code assigning it.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin Labbe <clabbe.montj...@gmail.com>
Acked-by: Corentin Labbe <clabbe.montj...@gmail.com>
---
drive
Cosmetic clean up if conditional checks on 0s values.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin Labbe <clabbe.montj...@gmail.com>
Acked-by: Corentin Labbe <clabbe.montj...@gmail.com>
---
drivers/crypto/sunxi-ss/sun4
Parts of the bf buffer were dynamically set to 0. Change this to set the
whole buffer to 0 by default to avoid any mistake.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin Labbe <clabbe.montj...@gmail.com>
Acked-by: Corentin Labbe <clabbe.mon
Add SoC specific compatibles for all sunXi crypto nodes, in addition to
the one already used (allwinner,sun4i-a10-crypto).
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 3 ++-
arch/arm/boot/dts/sun7i-a20.dtsi | 3 ++-
2 files chan
Update the sun4i-ss driver to use the skcipher API instead of the old
ablkcipher one. It's a bit more tricky than s/ablkcipher/skcipher/, but
still nothing special and the driver's logic stays the same.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin
Add a node for the cryptographic engine that can be found on sun5i SoCs.
This cryptographic engine is compatible with the Allwinner cryptographic
accelerator driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm/boot/dts/sun5i.dtsi | 9 +
1 file c
The CRYPTO_ALG_KERN_DRIVER_ONLY flag is set for hardware accelerated
ciphers accessible through a kernel driver only. This is the case for
ciphers exposed by the sun4i-ss driver. This patch sets this flag.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin
reading the computed digest to ensure it is
available in the SS_MD[] registers.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin Labbe <clabbe.montj...@gmail.com>
Acked-by: Corentin Labbe <clabbe.montj...@gmail.com>
---
drivers/crypto/sunxi-
When sending the last block of data to the engine, it should be padded
so that the total length of the request can be given to the engine as
the last 2 words of the last 64 bytes block.
Simplify the calculation of this pad offset.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.
nodes
Since v1:
- Fixed a typo.
- Made the CRYPTO_ALG_KERN_DRIVER_ONLY flag addition in a dedicated
patch.
Antoine Tenart (13):
crypto: sun4i-ss: group variable definitions in sun4i_hash()
crypto: sun4i-ss: remove conditional checks against 0
crypto: sun4i-ss: use lower/upper_32_bits
Cosmetic change to avoid having a full screen a variable definitions. It
also helps to see which variables share the same type.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin Labbe <clabbe.montj...@gmail.com>
Acked-by: Corentin Labbe &
Do not use DMA is the request is 0 length.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
Tested-by: Corentin Labbe <clabbe.montj...@gmail.com>
Acked-by: Corentin Labbe <clabbe.montj...@gmail.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 2 +-
1 file ch
Increase the batch size to the maximum number of requests a ring can
handle at a time (its size). This is possible now that the request
queues are per hw ring. This improves performances.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-
rypto engine driver").
I'd like to thank Ofer Heifetz and Igal Liberman who helped making
these changes!
Thanks,
Antoine
Antoine Tenart (10):
crypto: inside-secure - use hmac ipad/opad constants
crypto: inside-secure - fix the ring wr_cache offset
crypto: inside-secure - fix incorrect DSE
ombine these 2-3
updates into one large write transfer, generally improving performance.
Signed-off-by: Igal Liberman <ig...@marvell.com>
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-secure/safexcel.c | 1 +
drivers/crypto/inside-secure/s
Update the inside-secure safexcel driver from using one global queue to
one queue per hw ring. This ease the request management and keep the hw
in sync with what's done in sw.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-secure/safe
This update the dequeue function of the inside-secure safexcel driver so
that failed requests aren't requeued when they fail (for whatever
reason, which can be because the hw ring is full).
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-
Replace the hmac ipad/opad values by their defined constants.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-secure/safexcel_hash.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/crypto/inside-secure/safexcel_
This move the context and request updates at the end of the cipher and
hash send() functions. This way the context and request fields are set
only when everything else was successful in the send() functions.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/
Set the correct value to the DSE data cache, using WR_CACHE_3BITS
instead of RD_CACHE_3BITS. This fixes an incorrect setting and helps
improving performances.
Reported-by: Igal Liberman <ig...@marvell.com>
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
dr
This force the need_dequeue flag to be unset whenever the dequeue
function is called, to avoid calling it when it is not necessary.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/inside-secure/safexcel.c | 6 +++---
1 file changed, 3 insertions
From: Igal Liberman <ig...@marvell.com>
Configure the data write bufferability to always buffer packets in the
DSE. This change slightly improves performance.
Signed-off-by: Igal Liberman <ig...@marvell.com>
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
-
Hi Herbert,
On Wed, May 24, 2017 at 04:10:31PM +0200, Antoine Tenart wrote:
> The Inside Secure Safexcel cryptographic engine is found on some Marvell
> SoCs (7k/8k). Document the bindings used by its driver.
>
> Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.
Add a node for the cryptographic engine that can be found on sun5i SoCs.
This cryptographic engine is compatible with the Allwinner cryptographic
accelerator driver.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
arch/arm/boot/dts/sun5i.dtsi | 8
1 file chan
reading the computed digest to ensure it is
available in the SS_MD[] registers.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/crypto/sunxi-ss/su
Update the sun4i-ss driver to use the skcipher API instead of the old
ablkcipher one. It's a bit more tricky than s/ablkcipher/skcipher/, but
still nothing special and the driver's logic stays the same.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/su
Use the GENMASK helper instead of custom calculations to generate masks,
It also helps the readability.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff
Parts of the bf buffer were dynamically set to 0. Change this to set the
whole buffer to 0 by default to avoid any mistake.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Cosmetic clean up if conditional checks on 0s values.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-cipher.c | 28 +++---
drivers/crypto/sunxi-ss/sun4i-ss-core.c | 10
drivers/crypto/sunxi-ss/sun4i-ss-
Cosmetic change to avoid having a full screen a variable definitions. It
also helps to see which variables share the same type.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 31 +++
1 file chang
Replace custom bit shifts and masks with lower/upper_32_bits helpers.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/sunxi-ss/su
Antoine Tenart (11):
crypto: sun4i-ss: group variable definitions in sun4i_hash()
crypto: sun4i-ss: remove conditional checks against 0
crypto: sun4i-ss: use lower/upper_32_bits helpers
crypto: sun4i-ss: cannot use DMA is the request is 0 length
crypto: sun4i-ss: do not dynamically set
A bit is appended at the end of the input buffer for sha1. Simplify the
code assigning it.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/
Do not use DMA is the request is 0 length.
Signed-off-by: Antoine Tenart <antoine.ten...@free-electrons.com>
---
drivers/crypto/sunxi-ss/sun4i-ss-hash.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-hash.c
b/drivers/crypto/sunxi-ss/su
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