ZCB zeros the 128-byte cache block containing the base address.
Model the user-mode-visible effect by aligning the address down to a
128-byte line and storing sixteen zero doublewords to guest memory.
Signed-off-by: James Hilliard
---
Changes v2 -> v3:
- Split ZCB out of the combined Octeon arithmetic and memory
instruction patch. (requested by Richard Henderson)
---
target/mips/tcg/octeon.decode | 3 +++
target/mips/tcg/octeon_translate.c | 24
2 files changed, 27 insertions(+)
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
index d77717cd50..d8a1bfce77 100644
--- a/target/mips/tcg/octeon.decode
+++ b/target/mips/tcg/octeon.decode
@@ -49,6 +49,9 @@ SNEI 011100 rs:5 rt:5 imm:s10 10 &cmpi
SAA 011100 . . 0 0 011000 @saa
SAAD 011100 . . 0 0 011001 @saa
+&zcb base
+ZCB 011100 base:5 0 0 11100 01 &zcb
+
&lx base index rd
@lx .. base:5 index:5 rd:5 .. . &lx
LWX 01 . . . 0 001010 @lx
diff --git a/target/mips/tcg/octeon_translate.c
b/target/mips/tcg/octeon_translate.c
index 2a3f502e1f..794c8f033b 100644
--- a/target/mips/tcg/octeon_translate.c
+++ b/target/mips/tcg/octeon_translate.c
@@ -179,6 +179,30 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp
mop)
return true;
}
+static bool trans_ZCB(DisasContext *ctx, arg_zcb *a)
+{
+TCGv_i64 addr = tcg_temp_new_i64();
+TCGv_i64 line = tcg_temp_new_i64();
+TCGv_i64 zero = tcg_constant_i64(0);
+
+gen_base_offset_addr(ctx, addr, a->base, 0);
+
+/*
+ * QEMU models ZCB/ZCBT as zeroing the containing 128-byte cache line
+ * in guest memory.
+ */
+tcg_gen_andi_i64(line, addr, ~0x7fULL);
+
+for (int i = 0; i < 16; i++) {
+TCGv_i64 slot = tcg_temp_new_i64();
+
+tcg_gen_addi_i64(slot, line, i * 8);
+tcg_gen_qemu_st_i64(zero, slot, ctx->mem_idx, mo_endian(ctx) | MO_UQ);
+}
+
+return true;
+}
+
TRANS(SAA, trans_saa, MO_UL);
TRANS(SAAD, trans_saa, MO_UQ);
TRANS(LBX, trans_lx, MO_SB);
--
2.54.0
