>From FreeBSD (r227593, r307982): More and more RealTek controllers started to implement EEE feature. Vendor driver seems to load a kind of firmware for EEE with additional PHY fixups. It is known that the EEE feature may need ASPM support. Unfortunately there is no documentation for EEE of the controller so enabling ASPM may cause more problems.
The Realtek vendor driver [1] also disables ASPM and clock request. While here, add a define for the ECPM (Enable Clock Power Management) bit. Tested with: re0 at pci3 dev 0 function 0 "Realtek 8168" rev 0x0c: RTL8168G/8111G (0x4c00), msi, address 44:8a:5b:39:0a:25 rgephy0 at re0 phy 7: RTL8251 PHY, rev. 0 re0 at pci2 dev 0 function 0 "Realtek 8168" rev 0x03: RTL8168D/8111D (0x2800), msi, address bc:ae:c5:d6:ac:a3 rgephy0 at re0 phy 7: RTL8169S/8110S/8211 PHY, rev. 2 [1] http://www.realtek.com.tw/downloads/downloadsView.aspx?Langid=1&PNid=13&PFid=5&Level=5&Conn=4&DownTypeID=3&GetDown=false#2 Index: sys/dev/ic/rtl81x9reg.h =================================================================== RCS file: /cvs/src/sys/dev/ic/rtl81x9reg.h,v retrieving revision 1.100 diff -u -p -u -p -r1.100 rtl81x9reg.h --- sys/dev/ic/rtl81x9reg.h 16 Nov 2016 01:27:45 -0000 1.100 +++ sys/dev/ic/rtl81x9reg.h 17 May 2017 07:36:29 -0000 @@ -863,6 +863,7 @@ struct rl_softc { bus_space_handle_t rl_bhandle; /* bus space handle */ bus_space_tag_t rl_btag; /* bus space tag */ bus_dma_tag_t sc_dmat; + u_int32_t rl_expcap; bus_dma_segment_t sc_rx_seg; bus_dmamap_t sc_rx_dmamap; struct arpcom sc_arpcom; /* interface info */ Index: sys/dev/pci/if_re_pci.c =================================================================== RCS file: /cvs/src/sys/dev/pci/if_re_pci.c,v retrieving revision 1.50 diff -u -p -u -p -r1.50 if_re_pci.c --- sys/dev/pci/if_re_pci.c 28 Dec 2015 05:49:15 -0000 1.50 +++ sys/dev/pci/if_re_pci.c 17 May 2017 07:36:29 -0000 @@ -128,6 +128,7 @@ re_pci_attach(struct device *parent, str pci_chipset_tag_t pc = pa->pa_pc; pci_intr_handle_t ih; const char *intrstr = NULL; + pcireg_t reg; pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); @@ -172,8 +173,16 @@ re_pci_attach(struct device *parent, str * PCI Express check. */ if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, - NULL, NULL)) + &sc->rl_expcap, NULL)) { + /* Disable PCIe ASPM and ECPM. */ + reg = pci_conf_read(pc, pa->pa_tag, + sc->rl_expcap + PCI_PCIE_LCSR); + reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 | + PCI_PCIE_LCSR_ECPM); + pci_conf_write(pc, pa->pa_tag, + sc->rl_expcap + PCI_PCIE_LCSR, reg); sc->rl_flags |= RL_FLAG_PCIE; + } if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK && PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139)) { Index: sys/dev/pci/pcireg.h =================================================================== RCS file: /cvs/src/sys/dev/pci/pcireg.h,v retrieving revision 1.53 diff -u -p -u -p -r1.53 pcireg.h --- sys/dev/pci/pcireg.h 25 Mar 2017 07:33:46 -0000 1.53 +++ sys/dev/pci/pcireg.h 17 May 2017 07:36:29 -0000 @@ -574,6 +574,7 @@ typedef u_int8_t pci_revision_t; #define PCI_PCIE_LCSR_ASPM_L0S 0x00000001 #define PCI_PCIE_LCSR_ASPM_L1 0x00000002 #define PCI_PCIE_LCSR_ES 0x00000080 +#define PCI_PCIE_LCSR_ECPM 0x00000100 #define PCI_PCIE_SLCAP 0x14 #define PCI_PCIE_SLCAP_ABP 0x00000001 #define PCI_PCIE_SLCAP_PCP 0x00000002
