From: [EMAIL PROTECTED] Date: Tue, 7 Oct 2003 20:04:50 EDT
--So here is my new challenge regarding 6100 memory.
I have found 256 MB SIMMs that may work in a 6100. They are $60 each. I will have to sell my 4 of my 6 - 128's to cover the cost of the new SIMMs to pay for this experiment.
The spec's are:
72 pin, 256 MB Chip config: 16x32, 8 chips EDO, 60ns Non Parity 4k Refresh rate
The spec's look similar to the 128's I'm using. If they work, that gives the old 6100 520MB RAM!!
Should I go for it (rhetorical question)?
Can you get the manufacturer part number off of the chips from the seller? Or the chip configuration? Does 16 X 32 mean 16M X 32? That doesn't sound quite right. That would be 64 MB per chip and times 8 chips would be 512 MB, not 256 MB. Additionally, if the chips output 32 bits at a time, there would need to be additional logic on the board to split the addresses amongst them, unless they built a four or eight bank SIMM, which most likely would not be supported.
Anyway, with the chip part number, we could probably find what addressing mode is required by these chips and compare it to the information in Apple's "PowerMac_Computers.pdf", "RAM Expansion SIMMs" section. Unfortunately, the information in that section is not quite as detailed as in some others of Apple's Hardware Developer Notes documents.
The table in that section shows Row/Column addressing modes of 12/10 and 11/11 which supports 4 million addresses on a SIMM (22 address bits gives ~4 million addresses, 2^22 = 4M). Further, in the section "Hardware Overview/Functional Units--Main Circuit Board/Random-Access Memory" it states, "Each SIMM contains two banks of DRAM with up to 16 MB of capacity per bank," which is clearly wrong, since that would limit each SIMM to only 32 MB and you've used up to 128 MB in the 6100. But I think we can trust the two banks part.
So, 4 million addresses times 32 bits per address is 4M X 4 = 16MB. And with two banks that would be 32 MB. You've clearly used SIMMs larger than 32 MB, so the table showing up to 4M addresses must be incomplete.
If we assume the theoretical limit, there are 12 address lines listed in the SIMM's pinout in table 4-7, "RAM SIMM Pin Assignments". Twelve row addresses and twelve column addresses would give 24 address bits or 16M addresses, assuming this mode is supported by the memory controller. 16M X 4 bytes = 64 MB. And 2 banks per SIMM gives 128 MB, which is what you are using now.
This would appear to be the theoretical limit for the 72 pin SIMM in the x100, unless there is an undocumented address pin implemented in the SIMM sockets.
Pins 35 through 38 and 67 through 71 on the SIMM are "Reserved". So, one of those could be used as an additional address pin, but you'd need to take an ohmmeter to your SIMM socket and HMC chip to confirm or deny. And it is made more difficult because I don't think any of us knows which pins on the HMC would be used for addresses.
You might ask the SIMM vendor which pin on the SIMM is being used for A12. Assuming a numbering system of A[0] - A[11] for the documented address pins, then the additional necessary pin would be A[12]. If they're using A[1] - A[12], then in their notation they'd be calling it A[13], but the former notation is much more common.
I hope that helps. If any of it is unclear, feel free to question. I'm on digest so my replies are delayed a bit.
Jeff Walther
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