> These two set of resources can be "attached" to each other in a number > of different ways (e.g. L1 could be the only per-core cache or L2 > could also be per-core, etc.) and the job of a scheduler is to figure > out the best mapping of tasks to compute resources based on > alignment constraints. Paul had a nice post on these constraints > earlier. Here's an old post from Ingo outlining what is NOT free > with HyperThreading: > http://lwn.net/Articles/8553/
in my performace testing, try and theorize as i might, i have not yet been able to see l2 or other cache effects on intel machines. i may have seen l1 cache effects, but i rather think the reason that pinning the process to a cpu helped was that it was being scheduled when it wasn't needed on the other cpu. (that is, the design was wrong anway.) what i have seen is that the intel 82598 10gbit chip, by keeping its tx and rx descriptor rings in cachable regular memory can mash the fsb to little bits. it's still pretty fast, though. there's no use going fast, if you have no data to go fast on. - erik
