On Wed, 05 Sep 2018 07:42:52 -0400 Chris McGee <newton...@gmail.com> wrote:
> It could be, but after having looked briefly at the size of the design for
> RISC-V Rocket and especially BOOM I wonder if it's all overly complicated.
> They even built their own high level hardware language (Chisel) that
> generates Verilog using Scala. Yuck.

These are just tools.  By embedding Chisel in Scala they can
take advantage of Scala's strong typing etc. By generating
verilog they can advantage of existing tool chains to produce
an FPGA or ASIC or for simulation.  The h/w design tool chains
are pretty complex.  Hard to imagine any organization has a
stomach to replace them with something simpler. You can still
produce simple hardware design.

> Also, there's appears to be quite alot of compiler optimizations in gcc for
> RISC-based chips.

If you don't do this, cpu resources are not used efficiently.

H/W can provide a lot of computing resources that can be used
in parallel but none of the programming languages in use
provide a way to get to them effectively.

Part of the difficulty is that C/C++ are too low level and
their processor "model" is no longer the reality. Modern
CPUs have 2-3 levels of caching, TLBs etc.

> Could you get away with a much simpler, smaller hardware design and still
> run Plan 9 in a reasonable way? Maybe one side of the software/hardware
> divide has to take on more complexity to help simplify the other side?

Look at what Prof. Nicklaus Wirth did for Oberon.

But if all you want to do is just run plan9 why even bother?

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