Re: [9fans] Plan 9 C compiler for Xtensa CPUs

[Lucio De Re]

On 8/7/19, Charles Forsyth <charles.fors...@gmail.com> wrote:
> I've not previously seen an architecture where so many cache and TLB
> control instructions were in the primary space and took up so much of it.
>
I guess the remainder is RISC :-).

Lucio.