[email protected]: > you can't avoid M mode on riscv, ever. There are several trap cases that > will drop you in to M mode.
I thought avoiding M mode was forced on you by the SBI implementation (firmware), which intercepts M mode traps and delegates them to S mode (if it feels like it). That's my recollection from working with the Polarfire Icicle, but it's a few years back. Or are you designing for a bare metal platform with no SBI? Are there any riscv implementations on the market which allow kernel and user mode to run with different XLEN, and thus enable a 64-bit kernel to host 32-bit processes? If so, I think that implies that you would want user address space to start at (or near) zero. ------------------------------------------ 9fans: 9fans Permalink: https://9fans.topicbox.com/groups/9fans/Tf6e0b1b3f80df821-M5ca44f21c31403b6dd2a80b0 Delivery options: https://9fans.topicbox.com/groups/9fans/subscription
