Ronald G. Minnich was once rumoured to have said: > this is the ep93xx core. > > it all seems to be working with cache etc. Due to the fact that phsyical > memory is 4 segemnts at present only 16 MB of 32MB is usable.
This is the same problem that my current sparc32 code is plauged with -- each bank of physical ram on a SS10 appears on a 64MB boundary, so if a bank has less than 64MBs of RAM... > I also include a modified xalloc.c that lets you allocate "flavors" of > memory, e.g. uncached and cached regions. This may be handy at some point, > esp. when we get to 64-bit machines where at minimum you needed "low 4G" > and "above4G" flavors of memory. Actually, xalloc needs fixing to handle an arbitary number of physical ranges (rather than just the 2 it currently supports). I've been saying this on #plan9 for the past... umm... 3-4 weeks? I'll take a look at your code, try to remember how exactly I intended on patching xalloc before I forgot (I put it aside for one week too many) and see if I can fix it so we can use all the ram in both the SS10 and in the ts7200 as well... C.
