On Fri, Jan 15, 2010 at 04:05:27PM +0100, M vd S wrote: > Do we have exact information on this? I've seen several explanations. > > Let's try to get the picture complete, this is just a suggestion: > > clock_in(Kc,64) > clock_in(FN,22) > clock(100) > KS1 = clock_out(114) (downlink) > clock(100) > KS2 = clock_out(114) (uplink) > clock(100) > KS3 = clock_out(114) (downlink) > clock(100) > KS4 = clock_out(114) (uplink) > > ??
sequence is: clock_in(Kc, 64); clock_in(FN, 22); clock(100); KS1 = clock_out(114); KS2 = clock_out(114); clock_in(Kc, 64); clock_in(FN, 22); clock(100); KS3 = clock_out(114); KS4 = clock_out(114); source: various, never seen anything else. the reference implementation by briceno, goldberg and wagner also does not have 100 clocks between KS1 and KS2. first 114 bits are probably downlink (wikipedia). It should be noted that you get 51 + 114 64bit segments on an error free channel, because uplink continues where downlink ends. we are more interested in the downlink and should therefore not change our goal of 100 extra clockings. _______________________________________________ A51 mailing list [email protected] http://lists.lists.reflextor.com/cgi-bin/mailman/listinfo/a51
