Thank you for your answers. I have some more questions regarding the procedure.
1.There is a difference between the result from the demo and the code in reference/a51.cpp.The first bit in the 64bit keystream produced from the c++ code is the xor of the 19th,22nd,23rd bits whereas in the demo it is the xor after one clocking.Which one is the correct way? 2.Secondly in the demo the first bit of the keystream is in the msb of the keystream whereas in the a51.cpp it's in the lsb.Whick arrangement of bits in the keystream is the right one to xor with the round function?(I know it's just a demo and it's not maximum length either but been wondering about this because the next results will be different too.Is it right that whatever the arrangement of the bits with the proportional modification of the backlocking code will bear the same result internal state?) 3.What are the specifications of the lfsr used as a round function?I assume 64 bits maximum length,tap positions at 63,62,60,59 and initial value 0.If this is the case why the first result used to be xored with the keystream is FFFFFFFFFFFFFFF6 and not 0000000000000009?Shouldn't it be 9,c3,b6d and so on? 4. From your answer in my previous question i gather that if supposedly I have 0xde001bc0006f0000 as a starting point then the first result to be checked if it is a dp will be the (keystream generated by the a5/1 XOR the first round function value).However In the code the xor is applied before the a51 clockings so the first result checked(for run=nruns) is the (start point XOR rf) which is then loaded into the a51 registers.Which one is the first to be checked as a dp? 5.What do you mean in the code reverse the bit order to account for fpga optimization? I'm sorry for the long post.I would be grateful if you could answer any of my questions.Thank you again for your time.
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