On 05/16/2012 09:43 AM, Gordan Bobic wrote: > On 05/16/2012 04:34 PM, Stephen Warren wrote: >> On 05/16/2012 05:48 AM, Gordan Bobic wrote: >>> Had an interesting comment earlier: >>> >>> http://www.altechnative.net/2012/01/04/alleviating-memory-pressure-on-toshiba-ac100/#comment-1236 >>> >>> >>> >>> Is the BCT encoding of this information known/documented? >> >> I hope all the relevant registers are documented in the TRM (which >> despite the comment is indeed available to almost anyone; register to >> become a registered Tegra developer at >> http://developer.nvidia.com/tegra-2-technical-reference-manual) >> >> Then you'll need to correlate the BCT fields with those registers. I >> don't believe we document the BCT format anywhere at the moment. You >> might be able to work out the mapping by reading the field names in the >> cbootimage textual BCT format; see >> git://gitorious.org/trimslice-u-boot/trimslice-u-boot.git. Or trial and >> error with a JTAG probe. >> >> That all said, getting working SDRAM timing parameters for a new chip >> without support from the NVIDIA memqual people who do this for a living >> is likely to be extremely challenging. I would not recommend trying this. > > Hmm... I wonder if something like the T101 uses compatible chips. If > that was the case, we could pinch the relevant register settings from > the T101's BCT, and use the same chips it uses. And hope that the > difference in the board layout doesn't affect the timings...
I believe the board layout is extremely influential on the timings. _______________________________________________ Mailing list: https://launchpad.net/~ac100 Post to : [email protected] Unsubscribe : https://launchpad.net/~ac100 More help : https://help.launchpad.net/ListHelp
