http://bugzilla.kernel.org/show_bug.cgi?id=8956





------- Comment #38 from [EMAIL PROTECTED]  2007-09-29 21:56 -------
Several bugs report that I/O apic and timer can't be connected in the chipset
of NVIDIA. Maybe this is caused by the bug of Nvidia's chipset.
In theroy there are two pathes about the connection between timer and CPU.
a. connected to the pin 2 of I/O APIC.
b. connected to the pin 0 of I8259 and the output INTR pin of i8259 is
connected to the Pin 0 of I/O APIC and LINT0 of CPU local APIC.

In the initialization of the system the flowchart about the timer is listed in
the following:
1. Initialize the I8259 interrupt controller( the pic mode is used before I/O
APIC is enabled).
2. initialize the timer in the function of time_init and timer begins to work.
3. get the bogomips using the timer interrupt. 
4. change the timer route from i8259 to I/O APIC and check whether the timer
still works if I/O APIC is used.  If it can't work , the timer router will be
restored to i8259. 

On the chipset of Nvidia there are several phenomenas.
1. acpi=off, timer is connected to the pin 2 of I/O APIC and can work well.
   The route between timer and I/O APIC is defined in the MPS table and it is
correct.
2. noapic . timer is connected to the pin 0 of i8259 can work well. 
3. acpi=on, timer can work before I/O APIC is enabled. After the timer route is
changed to I/O APIC, the timer can't work. But when timer route is restored to
I8259, the timer still can't work. This is abnormal. 
   On the chipset of nvidia the route between timer and I/O apci isn't defined
correctly in the APIC table. But it is strange that timer can't work after the
timer route is restored to the I8259.
Maybe there are two possible explanations:
   a. the I8259 can't work after I/O APIC is enabled.
   b. the connection between INTR of i8259 can LINT0 of CPU is cut off after
I/O APIC is enabled.

Because we can't get the specification of Nvidia chipset, we can't give the
reasonable explanations about this.


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