Am Freitag, 12. März 2004 10:52 schrieb Gilles Chanteperdrix: > Paolo Mantegazza wrote: > > Der Herr Hofrat wrote: > > Yours is the first case I step on such a problem with Celerons. > > What about IDE controllers bus mastering DMA ? Can't this be the cause > of big bus locks ?
Not if i understand the pci latency timer right. its 32 PCI-Cycles in my case - this time after the grant a DMA master had to give away the bus. So the maximum latency is number of posible dma-masters * latency timer. calculating this on a 33 MHz bus is under 1 microsecond. I am unsure for how long the CPU can hold the Bus. And my IDE controler is not using DMA. And on the other Hand what has the ParPort to do with teh PCI bus ? Dirk
