Jan Kiszka wrote: > i386 port of the earlier posted x86_64 patch. > The usual mistake...
--- arch/i386/kernel/ipipe.c | 22 ++++++++------- include/asm-i386/ipipe.h | 65 +++++++++++++++++++++++++++-------------------- 2 files changed, 50 insertions(+), 37 deletions(-)
Index: linux-2.6.23.12-xeno/arch/i386/kernel/ipipe.c
===================================================================
--- linux-2.6.23.12-xeno.orig/arch/i386/kernel/ipipe.c
+++ linux-2.6.23.12-xeno/arch/i386/kernel/ipipe.c
@@ -764,17 +764,19 @@ int __ipipe_handle_irq(struct pt_regs re
finalize:
- /* Given our deferred dispatching model for regular IRQs, we
- * only record CPU regs for the last timer interrupt, so that
- * the timer handler charges CPU times properly. It is assumed
- * that other interrupt handlers don't actually care for such
- * information. */
-
+ /*
+ * Given our deferred dispatching model for regular IRQs, we only
+ * record relevant registers for the last timer interrupt, so that the
+ * timer handler charges CPU times properly. It is assumed that other
+ * interrupt handlers don't actually care for such information.
+ */
if (irq == __ipipe_tick_irq) {
- __raw_get_cpu_var(__ipipe_tick_regs).eflags = regs.eflags;
- __raw_get_cpu_var(__ipipe_tick_regs).eip = regs.eip;
- __raw_get_cpu_var(__ipipe_tick_regs).xcs = regs.xcs;
- __raw_get_cpu_var(__ipipe_tick_regs).ebp = regs.ebp;
+ struct pt_regs *tick_regs =
+ &__raw_get_cpu_var(__ipipe_tick_regs);
+ tick_regs->eflags = regs.eflags;
+ tick_regs->xcs = regs.xcs;
+ tick_regs->eip = regs.eip;
+ tick_regs->ebp = regs.ebp;
}
/*
Index: linux-2.6.23.12-xeno/include/asm-i386/ipipe.h
===================================================================
--- linux-2.6.23.12-xeno.orig/include/asm-i386/ipipe.h
+++ linux-2.6.23.12-xeno/include/asm-i386/ipipe.h
@@ -123,27 +123,40 @@ extern int __ipipe_tick_irq;
DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
-#define __ipipe_call_root_xirq_handler(ipd,irq) \
- __asm__ __volatile__ ("pushfl\n\t" \
- "pushl %%cs\n\t" \
- "pushl $1f\n\t" \
- "pushl %%eax\n\t" \
- "pushl %%fs\n\t" \
- "pushl %%es\n\t" \
- "pushl %%ds\n\t" \
- "pushl %%eax\n\t" \
- "pushl %%ebp\n\t" \
- "pushl %%edi\n\t" \
- "pushl %%esi\n\t" \
- "pushl %%edx\n\t" \
- "pushl %%ecx\n\t" \
- "pushl %%ebx\n\t" \
- "movl %%esp,%%eax\n\t" \
- "call *%1\n\t" \
- "jmp ret_from_intr\n\t" \
- "1: cli\n" \
- : /* no output */ \
- : "a" (~irq), "m" ((ipd)->irqs[irq].handler))
+static inline void
+__ipipe_call_root_xirq_handler(unsigned irq,
+ void (*handler)(unsigned irq, void *cookie))
+{
+ struct pt_regs *regs = &__raw_get_cpu_var(__ipipe_tick_regs);
+
+ regs->orig_eax = ~irq;
+
+ __asm__ __volatile__ (
+ "pushfl\n\t"
+ "pushl %%cs\n\t"
+ "pushl $xirq_end\n\t"
+ "pushl %%eax # dummy value\n\t"
+ "pushl %%fs\n\t"
+ "pushl %%es\n\t"
+ "pushl %%ds\n\t"
+ "pushl %%eax\n\t"
+ "pushl %%ebp\n\t"
+ "pushl %%edi\n\t"
+ "pushl %%esi\n\t"
+ "pushl %%edx\n\t"
+ "pushl %%ecx\n\t"
+ "pushl %%ebx\n\t"
+
+ "movl %[regs],%%eax # always pass tick regs\n\t"
+ "call *%[handler]\n\t"
+
+ "jmp ret_from_intr # Linux IRQ epilogue\n\t"
+
+ "xirq_end: cli\n\t"
+ : /* no output */ \
+ : [handler] "rm" (handler), [regs] "rm" (regs)
+ : "eax");
+}
#define __ipipe_call_root_virq_handler(ipd,irq) \
__asm__ __volatile__ ("pushfl\n\t" \
@@ -189,12 +202,10 @@ static inline unsigned long __ipipe_ffnz
do { \
local_irq_enable_nohead(ipd); \
if (ipd == ipipe_root_domain) { \
- if (likely(!ipipe_virtual_irq_p(irq))) { \
- struct pt_regs *old_regs; \
- old_regs = set_irq_regs(&__raw_get_cpu_var(__ipipe_tick_regs)); \
- __ipipe_call_root_xirq_handler(ipd,irq); \
- set_irq_regs(old_regs); \
- } else { \
+ if (likely(!ipipe_virtual_irq_p(irq))) \
+ __ipipe_call_root_xirq_handler( \
+ irq, (ipd)->irqs[irq].handler); \
+ else { \
irq_enter(); \
__ipipe_call_root_virq_handler(ipd,irq); \
irq_exit(); \
signature.asc
Description: OpenPGP digital signature
_______________________________________________ Adeos-main mailing list [email protected] https://mail.gna.org/listinfo/adeos-main
