Philippe Gerum wrote:
>> (ipipe_check_context+0x94)
>> | +*func 0 find_next_bit+0xa (__next_cpu+0x1a)
>> | +*func 0 __next_cpu+0x9 (ipipe_check_context+0x88)
>> | +*func 0 find_next_bit+0xa (__next_cpu+0x1a)
>> | +*func 0 __next_cpu+0x9 (ipipe_check_context+0x88)
>> | +*func 0 find_next_bit+0xa (__next_cpu+0x1a)
>> | +*func 0 __next_cpu+0x9 (ipipe_check_context+0x88)
>> | +*func 0 find_next_bit+0xa (__next_cpu+0x1a)
>> | +*func 0 __next_cpu+0x9 (ipipe_check_context+0x88)
>> | +*func 0 find_first_bit+0xa (__first_cpu+0x12)
>> | +*func -1 __first_cpu+0x8 (ipipe_check_context+0x66)
>> | +*func -1 ipipe_check_context+0x14
>> (_spin_lock_irqsave+0x1e)
>> | +*func -1 _spin_lock_irqsave+0x12
>> (pci_bus_read_config_word+0x36)
>> | +*func -1 pci_bus_read_config_word+0x14
>> (__msi_set_enable+0x46)
>> | +*func -1 __msi_set_enable+0x14
>> (msi_set_mask_bits+0xd8)
>> | +*func -1 msi_set_mask_bits+0xe (unmask_msi_irq+0x17)
>> | +*func -1 unmask_msi_irq+0x9 (default_enable+0x1a)
>> | +*func -1 default_enable+0x9 (rt_enable_irq+0xe
Excuse my naive question: but for every MSI interrupts, we need to issue
a PCI read and look for some bits ? Is not this a bit insane ?
--
Gilles.
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