Yes, a processor may be doing more than caching, so "flushing cached writes" may be a bit simplistic in terms of what happens when Thread.MemoryBarrier is called. But, it only deals with ensuring what the processor may be doing, not with what the compiler is doing (or has done) with registers. i.e. MemoryBarrier will not flush the value of a register to RAM if the compiler has optimized use of a variable to that register, how would MemoryBarrier know how to do that?
On Mon, 9 Jul 2007 14:14:53 -0400, Scott Allen <[EMAIL PROTECTED]> wrote: >In the end I didn't think about caches and registers, but about publishing >writes for others to see *in a specific order*. That's all we need to >guarantee. =================================== This list is hosted by DevelopMentor® http://www.develop.com View archives and manage your subscription(s) at http://discuss.develop.com
