In other words, a logic circuit that compresses an arbitrary bit vector to 1 bit and back? I could do it if the NOR gates had time delays so I could transmit the data serially.
On Sun, Oct 10, 2021, 2:57 PM James Bowery <[email protected]> wrote: > Another kind of Kolmogorov Complexity prize (ie: the Hutter Prize) based > on the following: > > The challenge is to come up with a n-NOR network (n-inputs allowed for any > NOR) with a bit vector as parallel input and the same bit vector as > parallel output but with the requirement that at some point in the network, > it narrow down to a single wire connecting the input n-NOR network to the > output n-NOR network. > > The award metric is the graph complexity of the n-NOR network. > > I believe I've mentioned this idea before and repeat it here with added > precision. > *Artificial General Intelligence List <https://agi.topicbox.com/latest>* > / AGI / see discussions <https://agi.topicbox.com/groups/agi> + > participants <https://agi.topicbox.com/groups/agi/members> + > delivery options <https://agi.topicbox.com/groups/agi/subscription> > Permalink > <https://agi.topicbox.com/groups/agi/T728994814c1a40a0-Me37a4d6047734bb2846242f0> > ------------------------------------------ Artificial General Intelligence List: AGI Permalink: https://agi.topicbox.com/groups/agi/T728994814c1a40a0-M1b74d01036a92b7ee3f679b3 Delivery options: https://agi.topicbox.com/groups/agi/subscription
