Andrew,

We really can't have this discussion without you first reading the article
I posted *The Itanium Effect*, where I propose an upgraded FPGA
architecture that doesn't have the problems of present-day FPGAs.

On Mon, Aug 3, 2015 at 9:01 AM, J. Andrew Rogers <[email protected]> wrote:

>
> For many things, FPGAs are not much (if any) faster than highly optimized
> CPU code.
>

Of course you mean present-day FPGAs, that are lacking the things I discuss
in the paper I posted *The Itanium Effect*.


> There are certain code patterns for which they do offer excellent
> performance but those cases are more limited than I think many people
> assume. However, I can see a few use cases for the CPU+FPGA hybrids that
> Intel is building.
>

My proposal goes WAY beyond this. Given the internals of a coarse-grained
FPGA, why even have a CPU when, if that is what you want, you can simply
configure the FPGA to be a CPU.

>
> Most codes today are limited by memory bandwidth and latency, which an
> FPGA does not address.
>

Now, add thousands, perhaps tens of thousands of tiny memory modules to an
FPGA, With these all available to work independently, memory bandwidth
issues are blown away.

On a side note, in the early days of minicomputers I had the pleasure/pain
of working on a LINC-8, a computer that had two different instruction sets
that it could switch between. One instruction set was the PDP-8 instruction
set designed for general purpose computation, and the other instruction set
was the LINC instruction set designed for biological laboratory computing.
I implemented the DOS for these machines, that utilized a then-gigantic 32K
(Yes, that is K, not M or B) hard disk. Of course the DOS had to interface
with both instruction sets and run existing 4K code in its expansive 8K
RAM. The I/O support for the LINC instruction set resided in the upper 4K.
The first phase of the project was to crunch/optimize the existing I/O code
enough to insert a bootstrap loader for the DOS, whereupon much of the
remaining I/O code became overlays. This experience opened my eyes to
seeing that having a strong processor available (now, like an FPGA as I
described in my article) eliminated the needs for LOTS of other things.

Steve
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