I recently put together a human brain equivalent model that takes into
consideration several aspects of system performance to figure out what
kind of system configuration we would need to generate a human
equivalent structure (which I expect would actually be much smarter than
a human in practice).  For the purposes of real-world projections,
taking MIPS and GB in the abstract is nigh useless because there are a
slew of caveats as to how all these components actually perform in real
systems.

First, we balanced and normalized system memory requirements in terms of
size with instructions per second and memory bandwidth/latency.  For our
architecture/code, we got the following "normal" core:


1 BIPS 32-bit integer core attached to 10^9 bytes RAM assuming common
memory architectures.  This is an optimum balance of transistor
allocation for us.


This normal core turns out to be 10^-6 human equivalent in our model. If
you compare our normal core to real systems, you find that CPU
performance is substantially outstripping the memory performance we
require.  That said, such a system could be built in a few years simply
by tweaking existing generic cores commonly used for custom systems
(like ARM or MIPS) and connecting scads of them with a low-latency
multi-dimensional interconnect.  Since you could put a dozen of these
cores on a real chip, the trick would be the memory system and
interconnects for each of these cores.

In short, the CPU is almost where we need it to be now, but the memory
is still way behind the curve.  By the time memory catches up so that we
can have human equivalent intelligence, we'll have enough extra CPU that
we'll have human level intelligence that runs much faster than a normal
human.  Which is to say the curve will be more on the "fast and stupid"
side of the curve than the "slow but smart" side of the curve if
balanced for existing architectures.

Cheers,


-James Rogers
 [EMAIL PROTECTED]


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