The 50 got reached by the Aquarius project (Berkeley and later ISI) which ran the gamut from Prolog through optimizing Prolog compilers to Prolog hardware to a fairly hairy 2-level shared-memory multiprocessor system. My own system was on the simple end, with a fairly vanilla instruction set spec, mathematical semantics for the instructions, a word-level RTL, a bit-level RTL, circuit designs at module, gate, and switch levels, timing models ranging from clocked combinational to SPICE and layout models ranging from abstract graphs to CIF. There were a couple of different representations of the pipeline behavior as well. Luckily for my sanity, we never got into superscalar, out-of-order, or any of that stuff that's de rigeur in modern processors!
Josh On Sunday 11 March 2007 20:07, Russell Wallace wrote: > On 3/11/07, J. Storrs Hall, PhD. <[EMAIL PROTECTED]> wrote: > > The main problem with this is that it seems to assume that there is One > > True > > Knowledge Representation in the system. In the automatic microprocessor > > design stuff I was doing in the 90s, there were up to 50 different levels > > of > > representation, and never less than 10, and that was for something > > already formalized and nominally well-understood, a computer > > architecture. > > Out of curiosity, is there a list available? I could have named maybe 4 or > 5, didn't realize there were as many as 50. > > ----- > This list is sponsored by AGIRI: http://www.agiri.org/email > To unsubscribe or change your options, please go to: > http://v2.listbox.com/member/?list_id=303 ----- This list is sponsored by AGIRI: http://www.agiri.org/email To unsubscribe or change your options, please go to: http://v2.listbox.com/member/?list_id=303
