On Thu, Mar 29, 2007 at 04:46:59PM +0200, Jean-Paul Van Belle wrote: > Some random thoughts. > > Any RAM location can link to any other RAM location so there are more > interconnects.
Not so fast. Memory bandwidth is very limited (~20 GByte/s current, GDDR3/GPUs are much better, agreed), and the access pattern is not flat. Predictable and local accesses are preferred, whereas worst case can be as low as 5% of advertised peak. The difference between CPU speed and memory bandwidth growth is a linear semi-log plot, too. However, the limited fan-out factors are not a problem with active media and even simple packet-switched signalling mesh. Embedded DRAM, wide bus ALU (with in-register parallelism) meshed up with a packet-switched signalling fabric is the bee's knees -- but you can't buy these yet. > The structure of RAM can be described very succintly. RAM alone doesn't compute. Try hardware CAs. These are pretty regular, too, and actually pack a lot of punch, especially in 3d. (In fact, the best possible classical computational substrate is a molecular-cell CA). > A CPU has 800 million transistors - a much more generous instruction > set than our brain. I have absolutely no idea what you mean by this. I'm hazarding that you yourself don't, either. -- Eugen* Leitl <a href="http://leitl.org";>leitl</a> http://leitl.org ______________________________________________________________ ICBM: 48.07100, 11.36820 http://www.ativel.com 8B29F6BE: 099D 78BA 2FD3 B014 B08A 7779 75B0 2443 8B29 F6BE ----- This list is sponsored by AGIRI: http://www.agiri.org/email To unsubscribe or change your options, please go to: http://v2.listbox.com/member/?list_id=303
