The PTE macro was a bit of a mess. Every user of it had the PA handy. But they always converted to the PPN. Plus, x86's kpte_write() wasn't even using it.
It also didn't need to be in a kernel header, which was causing some collisions for some applications. The mmu header is so that userspace can be aware of their address space and walk their own page tables. PTE() was something that could build a page table entry, which they don't need. I didn't compile the RISC-V stuff. It's slowly rotting. Reinstall your kernel headers. Signed-off-by: Barret Rhoden <[email protected]> --- kern/arch/riscv/cboot.c | 4 ++-- kern/arch/riscv/mmu.h | 10 +++++++++- kern/arch/riscv/pmap_ops.h | 4 +++- kern/arch/riscv/ros/mmu.h | 3 --- kern/arch/x86/kpt.h | 2 +- kern/arch/x86/mmu.h | 10 +++++++++- kern/arch/x86/pmap64.c | 4 ++-- kern/arch/x86/ros/mmu64.h | 3 --- 8 files changed, 26 insertions(+), 14 deletions(-) diff --git a/kern/arch/riscv/cboot.c b/kern/arch/riscv/cboot.c index 6161de5f19c6..cd6717b474df 100644 --- a/kern/arch/riscv/cboot.c +++ b/kern/arch/riscv/cboot.c @@ -27,7 +27,7 @@ void pagetable_init(uint32_t memsize_mb, pte_t* l1pt, pte_t* l1pt_boot, uint64_t memsize = mem_size(memsize_mb); for(uint64_t pa = 0; pa < memsize+L1PGSIZE-1; pa += L1PGSIZE) { - pte_t pte = PTE(LA2PPN(pa), PTE_KERN_RW | PTE_E); + pte_t pte = build_pte(pa, PTE_KERN_RW | PTE_E); l1pt_boot[L1X(pa)] = pte; // identity mapping l1pt_boot[L1X(KERNBASE+pa)] = pte; // KERNBASE mapping @@ -48,7 +48,7 @@ void pagetable_init(uint32_t memsize_mb, pte_t* l1pt, pte_t* l1pt_boot, l1pt_boot[L1X(KERN_LOAD_ADDR)] = PTD(l2pt); for (uintptr_t pa = 0; pa < (uintptr_t)(-KERN_LOAD_ADDR); pa += L2PGSIZE) - l2pt[L2X(KERN_LOAD_ADDR+pa)] = PTE(LA2PPN(pa), PTE_KERN_RW | PTE_E); + l2pt[L2X(KERN_LOAD_ADDR+pa)] = build_pte(pa, PTE_KERN_RW | PTE_E); #else (void) l2pt; // don't need this for rv32 #endif diff --git a/kern/arch/riscv/mmu.h b/kern/arch/riscv/mmu.h index 5d046abe5bfc..a950613f4f20 100644 --- a/kern/arch/riscv/mmu.h +++ b/kern/arch/riscv/mmu.h @@ -1,4 +1,12 @@ #pragma once -/* til we remove this file, unless we have some kernel-only stuff later */ #include <ros/arch/mmu.h> + +#ifndef __ASSEMBLER__ + +static inline pte_t build_pte(uintptr_t pa, int flags) +{ + return LA2PPN(pa) << PTE_PPN_SHIFT | PGOFF(flags); +} + +#endif /* __ASSEMBLER__ */ diff --git a/kern/arch/riscv/pmap_ops.h b/kern/arch/riscv/pmap_ops.h index 22768dbbafd9..9fd78ef7dd74 100644 --- a/kern/arch/riscv/pmap_ops.h +++ b/kern/arch/riscv/pmap_ops.h @@ -4,6 +4,8 @@ * * Arch-specific operations for page tables and PTEs */ +#warning "These are the x86 ops. Adopt them for RISC-V" + #pragma once static inline bool pte_walk_okay(pte_t pte) @@ -70,7 +72,7 @@ static inline unsigned long pte_print(pte_t pte) static inline void pte_write(pte_t pte, physaddr_t pa, int settings) { - *(kpte_t*)pte = PTE(pa2ppn(pa), settings); + *(kpte_t*)pte = build_pte(pa, settings); } static inline void pte_clear_present(pte_t pte) diff --git a/kern/arch/riscv/ros/mmu.h b/kern/arch/riscv/ros/mmu.h index f6e5d9d647fe..9bdcaabb520f 100644 --- a/kern/arch/riscv/ros/mmu.h +++ b/kern/arch/riscv/ros/mmu.h @@ -79,9 +79,6 @@ // offset in page #define PGOFF(la) (((uintptr_t) (la)) & (PGSIZE-1)) -// construct PTE from PPN and flags -#define PTE(ppn, flags) ((ppn) << PTE_PPN_SHIFT | (flags)) - // construct PTD from physical address #define PTD(pa) (((uintptr_t)(pa) >> PGSHIFT << PTE_PPN_SHIFT) | PTE_T) diff --git a/kern/arch/x86/kpt.h b/kern/arch/x86/kpt.h index 56a584f32108..1af3d6e389eb 100644 --- a/kern/arch/x86/kpt.h +++ b/kern/arch/x86/kpt.h @@ -58,7 +58,7 @@ static inline void kpte_write(kpte_t *kpte, physaddr_t pa, int settings) { assert(!PGOFF(pa)); /* The arch-bits like PTE_D, PTE_PS, etc are all in the native KPT format */ - *kpte = pa | settings; + *kpte = build_kpte(pa, settings); } static inline void kpte_clear_present(kpte_t *kpte) diff --git a/kern/arch/x86/mmu.h b/kern/arch/x86/mmu.h index 5d046abe5bfc..4e1dc631d3d7 100644 --- a/kern/arch/x86/mmu.h +++ b/kern/arch/x86/mmu.h @@ -1,4 +1,12 @@ #pragma once -/* til we remove this file, unless we have some kernel-only stuff later */ #include <ros/arch/mmu.h> + +#ifndef __ASSEMBLER__ + +static inline kpte_t build_kpte(uintptr_t pa, int flags) +{ + return LA2PPN(pa) << PGSHIFT | PGOFF(flags); +} + +#endif /* __ASSEMBLER__ */ diff --git a/kern/arch/x86/pmap64.c b/kern/arch/x86/pmap64.c index f8ccc76dd937..7d9134522473 100644 --- a/kern/arch/x86/pmap64.c +++ b/kern/arch/x86/pmap64.c @@ -590,8 +590,8 @@ int arch_pgdir_setup(pgdir_t boot_copy, pgdir_t *new_pd) memset(ept, 0, PGSIZE); /* VPT and UVPT map the proc's page table, with different permissions. */ - kpt[PML4(VPT)] = PTE(LA2PPN(PADDR(kpt)), PTE_KERN_RW); - kpt[PML4(UVPT)] = PTE(LA2PPN(PADDR(kpt)), PTE_USER_RO); + kpt[PML4(VPT)] = build_kpte(PADDR(kpt), PTE_KERN_RW); + kpt[PML4(UVPT)] = build_kpte(PADDR(kpt), PTE_USER_RO); new_pd->kpte = kpt; new_pd->eptp = construct_eptp(PADDR(ept)); diff --git a/kern/arch/x86/ros/mmu64.h b/kern/arch/x86/ros/mmu64.h index 637d72c24356..84a494159abb 100644 --- a/kern/arch/x86/ros/mmu64.h +++ b/kern/arch/x86/ros/mmu64.h @@ -251,9 +251,6 @@ typedef struct x86_pgdir { #define PGOFF(la) ((uintptr_t)(la) & (PGSIZE - 1)) #define NPTENTRIES 512 -/* construct PTE from PPN and flags */ -#define PTE(ppn, flags) ((ppn) << PGSHIFT | PGOFF(flags)) - /* This is used in places (procinfo) meaning "size of smallest jumbo page" */ #define PTSIZE PML2_PTE_REACH -- 2.6.0.rc2.230.g3dd15c0 -- You received this message because you are subscribed to the Google Groups "Akaros" group. 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