On 2016-03-10 at 11:28 "'Kanoj Sarcar' via Akaros"
<[email protected]> wrote:
>
> MLX uses WC to write data payload into HCA buffers. The performance
> boost over UC/UC- is significant. PAT details are added as comments
> above pat_init() routine.
Nice find!
> +
> +void pat_init(void)
> +{
> + unsigned long patval;
> +
> + patval = read_msr(MSR_IA32_CR_PAT);
> + printk("PAT : origvalue = 0x%llx\n", patval);
> +
> + /* Clear PAT1/5 */
> + patval &= 0xFFFF00FFFFFF00FFULL;
> +
> + /* Set PAT1/5 to WC */
> + patval |= (1 << 8);
> + patval |= (1ULL << 40);
> +
> + printk("PAT : newvalue = 0x%llx\n", patval);
> + write_msr(MSR_IA32_CR_PAT, patval);
This is probably dangerous. Does the PAT MSR apply to all cores, or
just the calling core? I think it might be just the calling core, and
it's probably a bad idea to have the cores disagree on the PAT
settings.
It makes sense that we need a WC setting in PAT, and we don't have one
at boot-up. How about we do the PAT setup in __arch_pcpu_init()?
(using a helper like the one you've got sounds fine). I'd rather have
this taken care of in the main OS, since its something we need
regardless of the Linux drivers.
Also, do we need both PAT1 and PAT5 set to WT? Could we leave PAT 1 as
WT (so if you select PTE bits PTE_PWT you get WT) and set PAT 5 to WC
(bits PTE_PAT|PTE_PWT). I'm not particularly tied to any of the PAT
locations/numbers; I'm just trying to keep WT as an option in our PAT
table.
> +static unsigned long pgprot_val(int vmprot)
> +{
> + unsigned long prot = PTE_P | PTE_U | PTE_A;
> +
> + if (vmprot & PROT_WRITE)
> + prot |= PTE_W | PTE_D;
Just curious, why are PTE_A and PTE_D set?
It sounds like the main kernel would benefit from another helper for
mapping. We can add something like:
uintptr_t vmap_pmem_writecomb(uintptr_t paddr, size_t nr_bytes);
which will map [paddr, paddr + bytes) with the right flags to select
the right PAT, and return the kernel address of the mapping. If you
need this for a user address, then we'll need a bit more work.
Barret
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