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        Title           : Network Overhead Problem Statement
        Author(s)       : D. Otis
        Filename        : draft-otis-network-overhead-00.txt
        Pages           : 
        Date            : 27-Feb-02
        
System performance is often limited by an integrated device 
interconnect.  Process differences between logic and memory keep 
large-scale memory interconnects critical as Moore's Law surpasses 
the rate of packaging reductions.  Two areas are related to memory 
interconnect performance when handling network messaging: 
- Logic and memory state context switching 
- Reassembly of partial messages with bifurcation of payload

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