Now, I get static when using only the second DMA channel, as dma1=5, dma2=5, and no other errors. (The firstDMA channel does not work at all…) My investigation points to that there may be problems in the sample rate/filter divider calculations.
Could any knowledgeable person verify if this calculation incorrect or not:
/* set filter register */ div0 = 256 - 7160000*20/(8*82*runtime->rate);
Here is the text outlining the procedure from the Datasheet for ES1878:
This register controls the low-pass frequency of the switchcapacitor filters inside the ES1878. Generally, the filter rolloff should be positioned at 80% - 90% of the Sample_Rate/ 2 frequency. The ratio of the roll-off frequency to the filter clock frequency is 1:82. In other words, first determine the desired roll-off frequency by taking 80% of the Sample_Rate divided by 2, then multiply by 82 to find the desired Filter Clock frequency. Use the formula below to determine the closest divider: Filter_Clock_Frequency = 7.16 MHz / (256-Filter_Divider_Register)
Regards From Erik
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