On Thu, 26 Feb 2004, Gupta, Kshitij wrote:
> Hi,
> So does that mean that the __next period__ DMA transfer parameters
> should be set in the interrupt routine(end of transfer of one period). But
> to set the next DMA transfer params we must know the start address of the
> buffer which the middle layer has filled (and if the middle layer has filled
> up more than one buffers then this buffer should be at the head of the
> list).
> Also one more point is that the hardware provides us the mechanism of
> linking the DMA channels ( linking means that once one dma channel finishes
> the transfer other one starts automatically). So this feature provides us
> the facility of queuing up the DMA transfers.
> regards
> -kshitij
Basically, we only copy the soundcard hardware and old ISA DMA engine
which is same as for PCI hardware etc.
The buffer size is divided to subblocks (we call them periods). These
periods determine spaces between interrupts and it's not necessary that
buffer_size == period_size * N (where N is an integer). Some hardware
(like ISA DMA controllers) can do any period sizes.
So, simply program your DMA controller to runtime->dma_addr + offset
for actual period and next periods. If you allow to set any period size,
then you need also handle shifts (you can avoid this by settings
snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) ).
> ps: one more nasty question I wanted to ask on the list was about how much
> time does it take to write a driver(from scratch) with such a complex
> framework ;)...probably just sharing experiences....
One week with full debugging. And I don't think that coding drivers is
complex, but it's required to know what's going on in the midlevel code
and you need to know the Linux kernel side memory handling.
Jaroslav
-----
Jaroslav Kysela <[EMAIL PROTECTED]>
Linux Kernel Sound Maintainer
ALSA Project, SuSE Labs
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