IB1 registers: regCP_IB1_CMD_BUFSZ regCP_IB1_BASE_LO regCP_IB1_BASE_HI regCP_IB1_BUFSZ regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR
Above registers are part of the asic but not of
the offset file for gc_11_0_0_offset.h and hence
adding them.
Signed-off-by: Sunil Khatri <sunil.kha...@amd.com>
---
.../gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
index 4bff1ef8a9a6..a3bcdf632066 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
@@ -7085,10 +7085,18 @@
#define regCP_GE_MSINVOC_COUNT_LO_BASE_IDX
1
#define regCP_GE_MSINVOC_COUNT_HI
0x20a7
#define regCP_GE_MSINVOC_COUNT_HI_BASE_IDX
1
+#define regCP_IB1_CMD_BUFSZ
0x20c0
+#define regCP_IB1_CMD_BUFSZ_BASE_IDX
1
#define regCP_IB2_CMD_BUFSZ
0x20c1
#define regCP_IB2_CMD_BUFSZ_BASE_IDX
1
#define regCP_ST_CMD_BUFSZ
0x20c2
#define regCP_ST_CMD_BUFSZ_BASE_IDX
1
+#define regCP_IB1_BASE_LO
0x20cc
+#define regCP_IB1_BASE_LO_BASE_IDX
1
+#define regCP_IB1_BASE_HI
0x20cd
+#define regCP_IB1_BASE_HI_BASE_IDX
1
+#define regCP_IB1_BUFSZ
0x20ce
+#define regCP_IB1_BUFSZ_BASE_IDX
1
#define regCP_IB2_BASE_LO
0x20cf
#define regCP_IB2_BASE_LO_BASE_IDX
1
#define regCP_IB2_BASE_HI
0x20d0
@@ -7541,6 +7549,8 @@
#define regCP_MES_DOORBELL_CONTROL5_BASE_IDX
1
#define regCP_MES_DOORBELL_CONTROL6
0x2841
#define regCP_MES_DOORBELL_CONTROL6_BASE_IDX
1
+#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR
0x2842
+#define regCP_MES_DEBUG_INTERRUPT_INSTR_PNTR_BASE_IDX
1
#define regCP_MES_GP0_LO
0x2843
#define regCP_MES_GP0_LO_BASE_IDX
1
#define regCP_MES_GP0_HI
0x2844
--
2.34.1
