On Mon, Aug 4, 2025 at 9:58 AM Timur Kristóf <timur.kris...@gmail.com> wrote:
>
> Unlike later versions, UVD 3 has firmware validation.
> For this to work, the UVD should be powered up correctly.
>
> When DPM is enabled and the display clock is off,
> the SMU may choose a power state which doesn't power
> the UVD, which can result in failure to initialize UVD.
+ Christian, Leo
That doesn't seem right to me. IIRC, the driver always set the UVD
PLL directly on SI and I don't think SI supported any kind of UVD
power gating. I guess it's probably some sort of subtle sequencing
difference between radeon and amdgpu. Unless Christian or Leo have
any ideas, I think the patch is probably fine.
Alex
>
> Fixes: b38f3e80ecec ("drm amdgpu: SI UVD v3_1 (v2)")
> Signed-off-by: Timur Kristóf <timur.kris...@gmail.com>
> ---
> drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> index 5dbaebb592b3..9ad06c1e150d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
> @@ -633,6 +633,12 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block
> *ip_block)
> int r;
>
> uvd_v3_1_mc_resume(adev);
> + uvd_v3_1_enable_mgcg(adev, true);
> +
> + if (adev->pm.dpm_enabled)
> + amdgpu_dpm_enable_uvd(adev, true);
> + else
> + amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
>
> r = uvd_v3_1_fw_validate(adev);
> if (r) {
> @@ -640,9 +646,6 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block
> *ip_block)
> return r;
> }
>
> - uvd_v3_1_enable_mgcg(adev, true);
> - amdgpu_asic_set_uvd_clocks(adev, 53300, 40000);
> -
> uvd_v3_1_start(adev);
>
> r = amdgpu_ring_test_helper(ring);
> --
> 2.50.1
>
