On Mon, Aug 25, 2025 at 6:07 PM Timur Kristóf <timur.kris...@gmail.com> wrote:
>
> This commit adds the pixel_clock field to the display config
> struct so that power management (DPM) can use it.
>
> We currently don't have a proper bandwidth calculation on old
> GPUs with DCE 6-10 because dce_calcs only supports DCE 11+.
> So the power management (DPM) on these GPUs may need to make
> ad-hoc decisions for display based on the pixel clock.
>
> Also rename sym_clock to pixel_clock in dm_pp_single_disp_config
> to avoid confusion with other code where the sym_clock refers to
> the DisplayPort symbol clock.
>
> Signed-off-by: Timur Kristóf <timur.kris...@gmail.com>
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 1 +
> drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 2 +-
> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 +-
> drivers/gpu/drm/amd/include/dm_pp_interface.h | 1 +
> 4 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index e5771f490f2e..11b2ea6edf95 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -98,6 +98,7 @@ bool dm_pp_apply_display_requirements(
> const struct dm_pp_single_disp_config *dc_cfg =
>
> &pp_display_cfg->disp_configs[i];
> adev->pm.pm_display_cfg.displays[i].controller_id =
> dc_cfg->pipe_idx + 1;
> + adev->pm.pm_display_cfg.displays[i].pixel_clock =
> dc_cfg->pixel_clock;
> }
>
> amdgpu_dpm_display_configuration_change(adev,
> &adev->pm.pm_display_cfg);
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> index 13cf415e38e5..d50b9440210e 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
> @@ -164,7 +164,7 @@ void dce110_fill_display_configs(
> stream->link->cur_link_settings.link_rate;
> cfg->link_settings.link_spread =
> stream->link->cur_link_settings.link_spread;
> - cfg->sym_clock = stream->phy_pix_clk;
> + cfg->pixel_clock = stream->phy_pix_clk;
> /* Round v_refresh*/
> cfg->v_refresh = stream->timing.pix_clk_100hz * 100;
> cfg->v_refresh /= stream->timing.h_total;
> diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> index bf63da266a18..3b093b8699ab 100644
> --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h
> @@ -127,7 +127,7 @@ struct dm_pp_single_disp_config {
> uint32_t src_height;
> uint32_t src_width;
> uint32_t v_refresh;
> - uint32_t sym_clock; /* HDMI only */
> + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only:
> normalized) */
This one could probably stay sym_clock to avoid the extra churn, but
either way is fine with me. Series is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> struct dc_link_settings link_settings; /* DP only */
> };
>
> diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h
> b/drivers/gpu/drm/amd/include/dm_pp_interface.h
> index acd1cef61b7c..349544504c93 100644
> --- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
> @@ -65,6 +65,7 @@ struct single_display_configuration {
> uint32_t view_resolution_cy;
> enum amd_pp_display_config_type displayconfigtype;
> uint32_t vertical_refresh; /* for active display */
> + uint32_t pixel_clock; /* Pixel clock in KHz (for HDMI only:
> normalized) */
> };
>
> #define MAX_NUM_DISPLAY 32
> --
> 2.50.1
>
