On Mon, Aug 25, 2025 at 5:46 PM Timur Kristóf <timur.kris...@gmail.com> wrote:
>
> Some parts of the code base expect that MCLK switching is turned
> off when the vblank time is set to zero.
>
> According to pp_pm_compute_clocks the non-DC code has issues
> with MCLK switching with refresh rates over 120 Hz.
>
> Fixes: 841686df9f7d ("drm/amdgpu: add SI DPM support (v4)")
> Signed-off-by: Timur Kristóf <timur.kris...@gmail.com>
> ---
> drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> index db46fc0817a7..1e2aeea0b552 100644
> --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c
> @@ -3082,8 +3082,8 @@ static bool si_dpm_vblank_too_short(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
> - /* we never hit the non-gddr5 limit so disable it */
> - u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ?
> 450 : 0;
> + /* we never hit the non-gddr5 limit so disable it (but treat 0 as too
> short) */
> + u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ?
> 450 : 1;
Took me a while to wrap my head around this. It might be clearer to
just return early if the vblank_time is 0. That said, if there are no
displays attached there is no reason to not enable mclk switching.
Alex
>
> if (vblank_time < switch_limit)
> return true;
> --
> 2.50.1
>
