> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Tom St Denis
> Sent: Wednesday, August 03, 2016 11:52 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: StDenis, Tom
> Subject: [PATCH 4/6] drm/amd/amdgpu: Move VCE bypass after MGCG test
>
> Only issue bypass if MGCG enabled
NACK. We need this for Polaris right now since we don't enable CG yet and
setting bypass mode saves power.
Alex
>
> Signed-off-by: Tom St Denis <tom.stde...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index 9d1924e4e2bc..63c9efefa583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -769,12 +769,12 @@ static int vce_v3_0_set_clockgating_state(void
> *handle,
> bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
> int i;
>
> - if (adev->asic_type == CHIP_POLARIS10)
> - vce_v3_set_bypass_mode(adev, enable);
> -
> if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
> return 0;
>
> + if (adev->asic_type == CHIP_POLARIS10)
> + vce_v3_set_bypass_mode(adev, enable);
> +
> mutex_lock(&adev->grbm_idx_mutex);
> for (i = 0; i < 2; i++) {
> /* Program VCE Instance 0 or 1 if not harvested */
> --
> 2.9.2
>
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