We need to cache some additional values to handle SR-IOV
and PG.

Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7d30a8e..efbd9ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -770,6 +770,16 @@ struct amdgpu_scratch {
 /*
  * GFX configurations
  */
+#define AMDGPU_GFX_MAX_SE 4
+#define AMDGPU_GFX_MAX_SH_PER_SE 2
+
+struct amdgpu_rb_config {
+       uint32_t rb_backend_disable;
+       uint32_t user_rb_backend_disable;
+       uint32_t raster_config;
+       uint32_t raster_config_1;
+};
+
 struct amdgpu_gca_config {
        unsigned max_shader_engines;
        unsigned max_tile_pipes;
@@ -798,6 +808,8 @@ struct amdgpu_gca_config {
 
        uint32_t tile_mode_array[32];
        uint32_t macrotile_mode_array[16];
+
+       struct amdgpu_rb_config 
rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
 };
 
 struct amdgpu_cu_info {
-- 
2.5.5

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