From: Rex Zhu <[email protected]>

iceland use pptable v0.

Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Rex Zhu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 51 +++++++++++++++---------
 1 file changed, 33 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index f41cddf..b0c929dd 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -4233,18 +4233,26 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, 
struct amd_pp_clocks *clocks)
 {
        struct phm_ppt_v1_information *table_info =
                        (struct phm_ppt_v1_information *)hwmgr->pptable;
-       struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
+       struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table = NULL;
+       struct phm_clock_voltage_dependency_table *sclk_table;
        int i;
 
-       if (table_info == NULL)
-               return -EINVAL;
-
-       dep_sclk_table = table_info->vdd_dep_on_sclk;
-
-       for (i = 0; i < dep_sclk_table->count; i++) {
-               clocks->clock[i] = dep_sclk_table->entries[i].clk;
-               clocks->count++;
+       if (hwmgr->pp_table_version == PP_TABLE_V1) {
+               if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)
+                       return -EINVAL;
+               dep_sclk_table = table_info->vdd_dep_on_sclk;
+               for (i = 0; i < dep_sclk_table->count; i++) {
+                       clocks->clock[i] = dep_sclk_table->entries[i].clk;
+                       clocks->count++;
+               }
+       } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
+               sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;
+               for (i = 0; i < sclk_table->count; i++) {
+                       clocks->clock[i] = sclk_table->entries[i].clk;
+                       clocks->count++;
+               }
        }
+
        return 0;
 }
 
@@ -4266,17 +4274,24 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, 
struct amd_pp_clocks *clocks)
                        (struct phm_ppt_v1_information *)hwmgr->pptable;
        struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
        int i;
+       struct phm_clock_voltage_dependency_table *mclk_table;
 
-       if (table_info == NULL)
-               return -EINVAL;
-
-       dep_mclk_table = table_info->vdd_dep_on_mclk;
-
-       for (i = 0; i < dep_mclk_table->count; i++) {
-               clocks->clock[i] = dep_mclk_table->entries[i].clk;
-               clocks->latency[i] = smu7_get_mem_latency(hwmgr,
+       if (hwmgr->pp_table_version == PP_TABLE_V1) {
+               if (table_info == NULL)
+                       return -EINVAL;
+               dep_mclk_table = table_info->vdd_dep_on_mclk;
+               for (i = 0; i < dep_mclk_table->count; i++) {
+                       clocks->clock[i] = dep_mclk_table->entries[i].clk;
+                       clocks->latency[i] = smu7_get_mem_latency(hwmgr,
                                                dep_mclk_table->entries[i].clk);
-               clocks->count++;
+                       clocks->count++;
+               }
+       } else if (hwmgr->pp_table_version == PP_TABLE_V0) {
+               mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;
+               for (i = 0; i < mclk_table->count; i++) {
+                       clocks->clock[i] = mclk_table->entries[i].clk;
+                       clocks->count++;
+               }
        }
        return 0;
 }
-- 
2.5.5

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