In driver, we can't assume there were only 2 performance levels on VI. it was decided by atombios. e.g. there were 3 performance levels in HP atom bios.
Change-Id: Ia7645ca12018092c3e5870403abf3d7ba20dc801 Signed-off-by: Rex Zhu <[email protected]> --- drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 33 +++++++++++++----------- 1 file changed, 18 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c index b1c7751..5ba0e75 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c @@ -2523,13 +2523,17 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, (struct phm_ppt_v1_information *)(hwmgr->pptable); int32_t count; int32_t stable_pstate_sclk = 0, stable_pstate_mclk = 0; + uint32_t high_level; data->battery_state = (PP_StateUILabel_Battery == request_ps->classification.ui_label); - PP_ASSERT_WITH_CODE(smu7_ps->performance_level_count == 2, - "VI should always have 2 performance levels", - ); + if (smu7_ps->performance_level_count < 1) { + printk(KERN_ERR "No Valid powerstate in pptable\n"); + return -EINVAL; + } + + high_level = smu7_ps->performance_level_count - 1; max_limits = (PP_PowerSource_AC == hwmgr->power_source) ? &(hwmgr->dyn_state.max_clock_voltage_on_ac) : @@ -2595,7 +2599,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, hwmgr->platform_descriptor.overdriveLimit.engineClock); if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) - smu7_ps->performance_levels[1].engine_clock = + smu7_ps->performance_levels[high_level].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive; } @@ -2607,7 +2611,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, hwmgr->platform_descriptor.overdriveLimit.memoryClock); if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) - smu7_ps->performance_levels[1].memory_clock = + smu7_ps->performance_levels[high_level].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive; } @@ -2623,8 +2627,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, mclk = smu7_ps->performance_levels[0].memory_clock; if (disable_mclk_switching) - mclk = smu7_ps->performance_levels - [smu7_ps->performance_level_count - 1].memory_clock; + mclk = smu7_ps->performance_levels[high_level].memory_clock; if (sclk < minimum_clocks.engineClock) sclk = (minimum_clocks.engineClock > max_limits->sclk) ? @@ -2637,22 +2640,22 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, smu7_ps->performance_levels[0].engine_clock = sclk; smu7_ps->performance_levels[0].memory_clock = mclk; - smu7_ps->performance_levels[1].engine_clock = - (smu7_ps->performance_levels[1].engine_clock >= + smu7_ps->performance_levels[high_level].engine_clock = + (smu7_ps->performance_levels[high_level].engine_clock >= smu7_ps->performance_levels[0].engine_clock) ? - smu7_ps->performance_levels[1].engine_clock : + smu7_ps->performance_levels[high_level].engine_clock : smu7_ps->performance_levels[0].engine_clock; if (disable_mclk_switching) { - if (mclk < smu7_ps->performance_levels[1].memory_clock) - mclk = smu7_ps->performance_levels[1].memory_clock; + if (mclk < smu7_ps->performance_levels[high_level].memory_clock) + mclk = smu7_ps->performance_levels[high_level].memory_clock; smu7_ps->performance_levels[0].memory_clock = mclk; - smu7_ps->performance_levels[1].memory_clock = mclk; + smu7_ps->performance_levels[high_level].memory_clock = mclk; } else { - if (smu7_ps->performance_levels[1].memory_clock < + if (smu7_ps->performance_levels[high_level].memory_clock < smu7_ps->performance_levels[0].memory_clock) - smu7_ps->performance_levels[1].memory_clock = + smu7_ps->performance_levels[high_level].memory_clock = smu7_ps->performance_levels[0].memory_clock; } -- 1.9.1 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
