> -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf > Of Tom St Denis > Sent: Monday, November 14, 2016 1:58 PM > To: [email protected] > Cc: StDenis, Tom > Subject: [PATCH 2/2] drm/amd/amdgpu: Tidy up formatting in si_enums.h > > Clean up formatting/alignment in si_enums.h to make it > more presentable. > > Signed-off-by: Tom St Denis <[email protected]>
NACK on this one. It makes it harder to see which defines are related to which packets. Alex > --- > drivers/gpu/drm/amd/amdgpu/si_enums.h | 241 +++++++++++++++++----- > ------------ > 1 file changed, 121 insertions(+), 120 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h > b/drivers/gpu/drm/amd/amdgpu/si_enums.h > index fde2086246fa..8fd54f6cd4f0 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si_enums.h > +++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h > @@ -146,127 +146,128 @@ > #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 > #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 > > -#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ > - (((op) & 0xFF) << 8) | \ > +#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ > + (((op) & 0xFF) << 8) | \ > ((n) & 0x3FFF) << 16) > + > #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) > -#define PACKET3_NOP 0x10 > -#define PACKET3_SET_BASE 0x11 > -#define PACKET3_BASE_INDEX(x) ((x) << 0) > -#define PACKET3_CLEAR_STATE 0x12 > -#define PACKET3_INDEX_BUFFER_SIZE 0x13 > -#define PACKET3_DISPATCH_DIRECT 0x15 > -#define PACKET3_DISPATCH_INDIRECT 0x16 > -#define PACKET3_ALLOC_GDS 0x1B > -#define PACKET3_WRITE_GDS_RAM 0x1C > -#define PACKET3_ATOMIC_GDS 0x1D > -#define PACKET3_ATOMIC 0x1E > -#define PACKET3_OCCLUSION_QUERY 0x1F > -#define PACKET3_SET_PREDICATION 0x20 > -#define PACKET3_REG_RMW 0x21 > -#define PACKET3_COND_EXEC 0x22 > -#define PACKET3_PRED_EXEC 0x23 > -#define PACKET3_DRAW_INDIRECT 0x24 > -#define PACKET3_DRAW_INDEX_INDIRECT 0x25 > -#define PACKET3_INDEX_BASE 0x26 > -#define PACKET3_DRAW_INDEX_2 0x27 > -#define PACKET3_CONTEXT_CONTROL 0x28 > -#define PACKET3_INDEX_TYPE 0x2A > -#define PACKET3_DRAW_INDIRECT_MULTI 0x2C > -#define PACKET3_DRAW_INDEX_AUTO > 0x2D > -#define PACKET3_DRAW_INDEX_IMMD > 0x2E > -#define PACKET3_NUM_INSTANCES 0x2F > -#define PACKET3_DRAW_INDEX_MULTI_AUTO > 0x30 > -#define PACKET3_INDIRECT_BUFFER_CONST 0x31 > -#define PACKET3_INDIRECT_BUFFER 0x3F > -#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 > -#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 > -#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 > -#define PACKET3_WRITE_DATA 0x37 > -#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 > -#define PACKET3_MEM_SEMAPHORE 0x39 > -#define PACKET3_MPEG_INDEX 0x3A > -#define PACKET3_COPY_DW 0x3B > -#define PACKET3_WAIT_REG_MEM 0x3C > -#define PACKET3_MEM_WRITE 0x3D > -#define PACKET3_COPY_DATA 0x40 > -#define PACKET3_CP_DMA 0x41 > -# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) > -# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) > -# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) > -# define PACKET3_CP_DMA_CP_SYNC (1 << 31) > -# define PACKET3_CP_DMA_DIS_WC (1 << 21) > -# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) > -# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) > -# define PACKET3_CP_DMA_CMD_SAS (1 << 26) > -# define PACKET3_CP_DMA_CMD_DAS (1 << 27) > -# define PACKET3_CP_DMA_CMD_SAIC (1 << 28) > -# define PACKET3_CP_DMA_CMD_DAIC (1 << 29) > -# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) > -#define PACKET3_PFP_SYNC_ME 0x42 > -#define PACKET3_SURFACE_SYNC 0x43 > -# define PACKET3_DEST_BASE_0_ENA (1 << 0) > -# define PACKET3_DEST_BASE_1_ENA (1 << 1) > -# define PACKET3_CB0_DEST_BASE_ENA (1 << 6) > -# define PACKET3_CB1_DEST_BASE_ENA (1 << 7) > -# define PACKET3_CB2_DEST_BASE_ENA (1 << 8) > -# define PACKET3_CB3_DEST_BASE_ENA (1 << 9) > -# define PACKET3_CB4_DEST_BASE_ENA (1 << 10) > -# define PACKET3_CB5_DEST_BASE_ENA (1 << 11) > -# define PACKET3_CB6_DEST_BASE_ENA (1 << 12) > -# define PACKET3_CB7_DEST_BASE_ENA (1 << 13) > -# define PACKET3_DB_DEST_BASE_ENA (1 << 14) > -# define PACKET3_DEST_BASE_2_ENA (1 << 19) > -# define PACKET3_DEST_BASE_3_ENA (1 << 21) > -# define PACKET3_TCL1_ACTION_ENA (1 << 22) > -# define PACKET3_TC_ACTION_ENA (1 << 23) > -# define PACKET3_CB_ACTION_ENA (1 << 25) > -# define PACKET3_DB_ACTION_ENA (1 << 26) > -# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) > -# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) > -#define PACKET3_ME_INITIALIZE 0x44 > -#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) > -#define PACKET3_COND_WRITE 0x45 > -#define PACKET3_EVENT_WRITE 0x46 > -#define PACKET3_EVENT_WRITE_EOP 0x47 > -#define PACKET3_EVENT_WRITE_EOS 0x48 > -#define PACKET3_PREAMBLE_CNTL 0x4A > -# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) > -# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) > -#define PACKET3_ONE_REG_WRITE 0x57 > -#define PACKET3_LOAD_CONFIG_REG 0x5F > -#define PACKET3_LOAD_CONTEXT_REG 0x60 > -#define PACKET3_LOAD_SH_REG 0x61 > -#define PACKET3_SET_CONFIG_REG 0x68 > -#define PACKET3_SET_CONFIG_REG_START > 0x00002000 > -#define PACKET3_SET_CONFIG_REG_END > 0x00002c00 > -#define PACKET3_SET_CONTEXT_REG 0x69 > -#define PACKET3_SET_CONTEXT_REG_START > 0x000a000 > -#define PACKET3_SET_CONTEXT_REG_END > 0x000a400 > -#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 > -#define PACKET3_SET_RESOURCE_INDIRECT 0x74 > -#define PACKET3_SET_SH_REG 0x76 > -#define PACKET3_SET_SH_REG_START > 0x00002c00 > -#define PACKET3_SET_SH_REG_END > 0x00003000 > -#define PACKET3_SET_SH_REG_OFFSET 0x77 > -#define PACKET3_ME_WRITE 0x7A > -#define PACKET3_SCRATCH_RAM_WRITE 0x7D > -#define PACKET3_SCRATCH_RAM_READ 0x7E > -#define PACKET3_CE_WRITE 0x7F > -#define PACKET3_LOAD_CONST_RAM 0x80 > -#define PACKET3_WRITE_CONST_RAM 0x81 > -#define PACKET3_WRITE_CONST_RAM_OFFSET > 0x82 > -#define PACKET3_DUMP_CONST_RAM 0x83 > -#define PACKET3_INCREMENT_CE_COUNTER 0x84 > -#define PACKET3_INCREMENT_DE_COUNTER 0x85 > -#define PACKET3_WAIT_ON_CE_COUNTER 0x86 > -#define PACKET3_WAIT_ON_DE_COUNTER 0x87 > -#define PACKET3_WAIT_ON_DE_COUNTER_DIFF > 0x88 > -#define PACKET3_SET_CE_DE_COUNTERS 0x89 > -#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A > -#define PACKET3_SWITCH_BUFFER 0x8B > -#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) > -#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) > -#define PACKET3_SEM_SEL_WAIT (0x7 << 29) > +#define PACKET3_NOP 0x10 > +#define PACKET3_SET_BASE 0x11 > +#define PACKET3_BASE_INDEX(x) ((x) << 0) > +#define PACKET3_CLEAR_STATE 0x12 > +#define PACKET3_INDEX_BUFFER_SIZE 0x13 > +#define PACKET3_DISPATCH_DIRECT 0x15 > +#define PACKET3_DISPATCH_INDIRECT 0x16 > +#define PACKET3_ALLOC_GDS 0x1B > +#define PACKET3_WRITE_GDS_RAM 0x1C > +#define PACKET3_ATOMIC_GDS 0x1D > +#define PACKET3_ATOMIC 0x1E > +#define PACKET3_OCCLUSION_QUERY 0x1F > +#define PACKET3_SET_PREDICATION 0x20 > +#define PACKET3_REG_RMW 0x21 > +#define PACKET3_COND_EXEC 0x22 > +#define PACKET3_PRED_EXEC 0x23 > +#define PACKET3_DRAW_INDIRECT 0x24 > +#define PACKET3_DRAW_INDEX_INDIRECT 0x25 > +#define PACKET3_INDEX_BASE 0x26 > +#define PACKET3_DRAW_INDEX_2 0x27 > +#define PACKET3_CONTEXT_CONTROL 0x28 > +#define PACKET3_INDEX_TYPE 0x2A > +#define PACKET3_DRAW_INDIRECT_MULTI 0x2C > +#define PACKET3_DRAW_INDEX_AUTO 0x2D > +#define PACKET3_DRAW_INDEX_IMMD 0x2E > +#define PACKET3_NUM_INSTANCES 0x2F > +#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 > +#define PACKET3_INDIRECT_BUFFER_CONST 0x31 > +#define PACKET3_INDIRECT_BUFFER 0x3F > +#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 > +#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 > +#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 > +#define PACKET3_WRITE_DATA 0x37 > +#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 > +#define PACKET3_MEM_SEMAPHORE 0x39 > +#define PACKET3_MPEG_INDEX 0x3A > +#define PACKET3_COPY_DW 0x3B > +#define PACKET3_WAIT_REG_MEM 0x3C > +#define PACKET3_MEM_WRITE 0x3D > +#define PACKET3_COPY_DATA 0x40 > +#define PACKET3_CP_DMA 0x41 > +#define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) > +#define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) > +#define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) > +#define PACKET3_CP_DMA_CP_SYNC (1 << 31) > +#define PACKET3_CP_DMA_DIS_WC (1 << 21) > +#define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) > +#define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) > +#define PACKET3_CP_DMA_CMD_SAS (1 << 26) > +#define PACKET3_CP_DMA_CMD_DAS (1 << 27) > +#define PACKET3_CP_DMA_CMD_SAIC (1 << 28) > +#define PACKET3_CP_DMA_CMD_DAIC (1 << 29) > +#define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) > +#define PACKET3_PFP_SYNC_ME 0x42 > +#define PACKET3_SURFACE_SYNC 0x43 > +#define PACKET3_DEST_BASE_0_ENA (1 << 0) > +#define PACKET3_DEST_BASE_1_ENA (1 << 1) > +#define PACKET3_CB0_DEST_BASE_ENA (1 << 6) > +#define PACKET3_CB1_DEST_BASE_ENA (1 << 7) > +#define PACKET3_CB2_DEST_BASE_ENA (1 << 8) > +#define PACKET3_CB3_DEST_BASE_ENA (1 << 9) > +#define PACKET3_CB4_DEST_BASE_ENA (1 << 10) > +#define PACKET3_CB5_DEST_BASE_ENA (1 << 11) > +#define PACKET3_CB6_DEST_BASE_ENA (1 << 12) > +#define PACKET3_CB7_DEST_BASE_ENA (1 << 13) > +#define PACKET3_DB_DEST_BASE_ENA (1 << 14) > +#define PACKET3_DEST_BASE_2_ENA (1 << 19) > +#define PACKET3_DEST_BASE_3_ENA (1 << 21) > +#define PACKET3_TCL1_ACTION_ENA (1 << 22) > +#define PACKET3_TC_ACTION_ENA (1 << 23) > +#define PACKET3_CB_ACTION_ENA (1 << 25) > +#define PACKET3_DB_ACTION_ENA (1 << 26) > +#define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) > +#define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) > +#define PACKET3_ME_INITIALIZE 0x44 > +#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) > +#define PACKET3_COND_WRITE 0x45 > +#define PACKET3_EVENT_WRITE 0x46 > +#define PACKET3_EVENT_WRITE_EOP 0x47 > +#define PACKET3_EVENT_WRITE_EOS 0x48 > +#define PACKET3_PREAMBLE_CNTL 0x4A > +#define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) > +#define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) > +#define PACKET3_ONE_REG_WRITE 0x57 > +#define PACKET3_LOAD_CONFIG_REG 0x5F > +#define PACKET3_LOAD_CONTEXT_REG 0x60 > +#define PACKET3_LOAD_SH_REG 0x61 > +#define PACKET3_SET_CONFIG_REG 0x68 > +#define PACKET3_SET_CONFIG_REG_START 0x00002000 > +#define PACKET3_SET_CONFIG_REG_END 0x00002c00 > +#define PACKET3_SET_CONTEXT_REG 0x69 > +#define PACKET3_SET_CONTEXT_REG_START 0x000a000 > +#define PACKET3_SET_CONTEXT_REG_END 0x000a400 > +#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 > +#define PACKET3_SET_RESOURCE_INDIRECT 0x74 > +#define PACKET3_SET_SH_REG 0x76 > +#define PACKET3_SET_SH_REG_START 0x00002c00 > +#define PACKET3_SET_SH_REG_END 0x00003000 > +#define PACKET3_SET_SH_REG_OFFSET 0x77 > +#define PACKET3_ME_WRITE 0x7A > +#define PACKET3_SCRATCH_RAM_WRITE 0x7D > +#define PACKET3_SCRATCH_RAM_READ 0x7E > +#define PACKET3_CE_WRITE 0x7F > +#define PACKET3_LOAD_CONST_RAM 0x80 > +#define PACKET3_WRITE_CONST_RAM 0x81 > +#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 > +#define PACKET3_DUMP_CONST_RAM 0x83 > +#define PACKET3_INCREMENT_CE_COUNTER 0x84 > +#define PACKET3_INCREMENT_DE_COUNTER 0x85 > +#define PACKET3_WAIT_ON_CE_COUNTER 0x86 > +#define PACKET3_WAIT_ON_DE_COUNTER 0x87 > +#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 > +#define PACKET3_SET_CE_DE_COUNTERS 0x89 > +#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A > +#define PACKET3_SWITCH_BUFFER 0x8B > +#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) > +#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) > +#define PACKET3_SEM_SEL_WAIT (0x7 << 29) > > #endif > -- > 2.10.0 > > _______________________________________________ > amd-gfx mailing list > [email protected] > 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