Am 04.02.2017 um 05:51 schrieb Andres Rodriguez:
The CP_MEC_DOORBELL_RANGE_* and CP_PQ_STATUS.DOORBELL_ENABLE registers are not HQD specific.They only need to be set once if at least 1 pipe requested doorbell support. Signed-off-by: Andres Rodriguez <andre...@gmail.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 147ce0e..9740800 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1427,6 +1427,7 @@ struct amdgpu_device { unsigned num_rings; struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; bool ib_pool_ready; + bool doorbell_enabled;
Better put that into amdgpu_gfx and not amdgpu_device, cause that is a gfx (CP) specific state.
Apart from that the patch looks good to me. Christian.
struct amdgpu_sa_manager ring_tmp_bo;/* interrupts */diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index cf738e5..5d0e2c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4796,7 +4796,7 @@ static void gfx_v8_0_enable_doorbell(struct amdgpu_device *adev, bool enable) { uint32_t tmp;- if (!enable)+ if (!enable || adev->doorbell_enabled) return;if ((adev->asic_type == CHIP_CARRIZO) ||@@ -4811,6 +4811,8 @@ static void gfx_v8_0_enable_doorbell(struct amdgpu_device *adev, bool enable) tmp = RREG32(mmCP_PQ_STATUS); tmp = REG_SET_FIELD(tmp, CP_PQ_STATUS, DOORBELL_ENABLE, 1); WREG32(mmCP_PQ_STATUS, tmp); + + adev->doorbell_enabled = true; }static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev, struct vi_mqd *mqd)@@ -5108,6 +5110,8 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) { int r;+ adev->doorbell_enabled = false;+ if (!(adev->flags & AMD_IS_APU)) gfx_v8_0_enable_gui_idle_interrupt(adev, false);
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