> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, March 07, 2017 6:00 AM
> To: Andres Rodriguez; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 18/21] drm/amdgpu: add framework for HW specific
> priority settings v4
>
> Am 07.03.2017 um 02:10 schrieb Andres Rodriguez:
> > Add an initial framework for changing the HW priorities of rings. The
> > framework allows requesting priority changes for the lifetime of an
> > amdgpu_job. After the job completes the priority will decay to the next
> > lowest priority for which a request is still valid.
> >
> > A new ring function set_priority() can now be populated to take care of
> > the HW specific programming sequence for priority changes.
> >
> > v2: set priority before emitting IB, and take a ref on amdgpu_job
> > v3: use AMD_SCHED_PRIORITY_* instead of AMDGPU_CTX_PRIORITY_*
> > v4: plug amdgpu_ring_restore_priority_cb into amdgpu_job_free_cb
> > v5: use atomic for tracking job priorities instead of last_job
> >
> > Signed-off-by: Andres Rodriguez <andre...@gmail.com>
>
> Two more nit picks and one real problem below.
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 8 +++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 82
> +++++++++++++++++++++++++++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 15 +++++
> > drivers/gpu/drm/amd/scheduler/gpu_scheduler.h | 7 +++
> > 4 files changed, 112 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> > index 86a1242..bd6fa0f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> > @@ -88,20 +88,21 @@ void amdgpu_job_free_resources(struct
> amdgpu_job *job)
> > f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
> >
> > for (i = 0; i < job->num_ibs; ++i)
> > amdgpu_ib_free(job->adev, &job->ibs[i], f);
> > }
> >
> > static void amdgpu_job_free_cb(struct amd_sched_job *s_job)
> > {
> > struct amdgpu_job *job = container_of(s_job, struct amdgpu_job,
> base);
> >
> > + amdgpu_ring_restore_priority(job);
> > dma_fence_put(job->fence);
> > amdgpu_sync_free(&job->sync);
> > kfree(job);
> > }
> >
> > void amdgpu_job_free(struct amdgpu_job *job)
> > {
> > amdgpu_job_free_resources(job);
> >
> > dma_fence_put(job->fence);
> > @@ -162,28 +163,35 @@ static struct dma_fence *amdgpu_job_run(struct
> amd_sched_job *sched_job)
> > int r;
> >
> > if (!sched_job) {
> > DRM_ERROR("job is null\n");
> > return NULL;
> > }
> > job = to_amdgpu_job(sched_job);
> >
> > BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
> >
> > + r = amdgpu_ring_elevate_priority(job->ring,
> > + amd_sched_get_job_priority(&job-
> >base),
> > + job);
> > + if (r)
> > + DRM_ERROR("Failed to set job priority (%d)\n", r);
> > +
> > trace_amdgpu_sched_run_job(job);
> > r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job,
> &fence);
> > if (r)
> > DRM_ERROR("Error scheduling IBs (%d)\n", r);
> >
> > /* if gpu reset, hw fence will be replaced here */
> > dma_fence_put(job->fence);
> > job->fence = dma_fence_get(fence);
> > +
> > amdgpu_job_free_resources(job);
> > return fence;
> > }
> >
> > const struct amd_sched_backend_ops amdgpu_sched_ops = {
> > .dependency = amdgpu_job_dependency,
> > .run_job = amdgpu_job_run,
> > .timedout_job = amdgpu_job_timedout,
> > .free_job = amdgpu_job_free_cb
> > };
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > index d655fa4..d67dc69 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
> > @@ -193,20 +193,100 @@ void amdgpu_ring_commit(struct amdgpu_ring
> *ring)
> > */
> > void amdgpu_ring_undo(struct amdgpu_ring *ring)
> > {
> > ring->wptr = ring->wptr_old;
> >
> > if (ring->funcs->end_use)
> > ring->funcs->end_use(ring);
> > }
> >
> > /**
> > + * amdgpu_ring_restore_priority - restore a ring's priority
> > + *
> > + * @job: job which completed execution
> > + *
> > + * If necessary, restore a ring's priority after a job finishes executing
> > + */
> > +void amdgpu_ring_restore_priority(struct amdgpu_job *job)
>
> Only a nit pick. But just giving job_priority as parameter directly here
> would bring it in line with how amdgpu_ring_elevate_priority() works.
>
> > +{
> > + int i;
> > + struct amdgpu_ring *ring = job->ring;
> > + enum amd_sched_priority job_priority;
> > +
> > + if (!ring->funcs->set_priority)
> > + return;
> > +
> > + job_priority = amd_sched_get_job_priority(&job->base);
> > + if (atomic_dec_return(&ring->num_jobs[job_priority]) > 0)
> > + return;
> > +
> > + /* no need to restore if the job is already at the lowest priority */
> > + if (job_priority == AMD_SCHED_PRIORITY_NORMAL)
> > + return;
> > +
> > + spin_lock(&ring->priority_lock);
> > + /* something higher prio is executing, no need to decay */
> > + if (ring->priority < job_priority)
> > + goto out_unlock;
> > +
> > + /* decay priority to the next level with a job available */
> > + for (i = job_priority; i < AMD_SCHED_MAX_PRIORITY; i++) {
> > + if (i == AMD_SCHED_PRIORITY_NORMAL
> > + || atomic_read(&ring->num_jobs[i])) {
> > + ring->priority = i;
> > + ring->funcs->set_priority(ring, i);
> > + break;
> > + }
> > + }
> > +
> > +out_unlock:
> > + spin_unlock(&ring->priority_lock);
> > +}
> > +
> > +/**
> > + * amdgpu_ring_elevate_priority - change the ring's priority
> > + *
> > + * @ring: amdgpu_ring structure holding the information
> > + * @priority: target priority
> > + * @job: priority should remain elevated for the duration of this job
> > + *
> > + * Use HW specific mechanism's to elevate the ring's priority while @job
> > + * is executing. Once @job finishes executing, the ring will reset back
> > + * to normal priority.
> > + * Returns 0 on success, error otherwise
> > + */
> > +int amdgpu_ring_elevate_priority(struct amdgpu_ring *ring,
> > + enum amd_sched_priority priority,
> > + struct amdgpu_job *job)
>
> As far as I can see the job parameter is superfluous now.
>
> > +{
> > + if (priority < 0 || priority >= AMD_SCHED_MAX_PRIORITY)
> > + return -EINVAL;
> > +
> > + if (!ring->funcs->set_priority)
> > + return 0;
> > +
> > + atomic_inc(&ring->num_jobs[priority]);
> > +
> > + /* lower number means higher priority */
> > + spin_lock(&ring->priority_lock);
>
> Sorry, could be that I incorrectly suggested that. Double checking the
> set_priority callback you need to take the GRBM mutex to set the
> priority. Don't you?
>
> If that's true this would be illegal cause you take a spin lock first
> and then try to grab a mutex which can cause a deadlock.
>
> BTW: Alex, Felix does anybody of hand know why the GRBM lock is a mutex
> in the first place? Sounds scary to schedule while having the hardware
> in a very specific state.
IIRC, Initially we only used the grbm lock during init, so a mutex seemed
sufficient.
Alex
>
> Regards,
> Christian.
>
> > + if (priority >= ring->priority)
> > + goto out_unlock;
> > +
> > + ring->priority = priority;
> > + ring->funcs->set_priority(ring, priority);
> > +
> > +out_unlock:
> > + spin_unlock(&ring->priority_lock);
> > + return 0;
> > +}
> > +
> > +/**
> > * amdgpu_ring_init - init driver ring struct.
> > *
> > * @adev: amdgpu_device pointer
> > * @ring: amdgpu_ring structure holding ring information
> > * @max_ndw: maximum number of dw for ring alloc
> > * @nop: nop packet for this ring
> > *
> > * Initialize the driver information for the selected ring (all asics).
> > * Returns 0 on success, error on failure.
> > */
> > @@ -274,20 +354,22 @@ int amdgpu_ring_init(struct amdgpu_device
> *adev, struct amdgpu_ring *ring,
> > &ring->gpu_addr,
> > (void **)&ring->ring);
> > if (r) {
> > dev_err(adev->dev, "(%d) ring create failed\n", r);
> > return r;
> > }
> > memset((void *)ring->ring, 0, ring->ring_size);
> > }
> > ring->ptr_mask = (ring->ring_size / 4) - 1;
> > ring->max_dw = max_dw;
> > + ring->priority = AMD_SCHED_PRIORITY_NORMAL;
> > + spin_lock_init(&ring->priority_lock);
> > INIT_LIST_HEAD(&ring->lru_list);
> > amdgpu_ring_lru_touch(adev, ring);
> >
> > if (amdgpu_debugfs_ring_init(adev, ring)) {
> > DRM_ERROR("Failed to register debugfs file for rings !\n");
> > }
> > return 0;
> > }
> >
> > /**
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > index b51bdcd..bad40f8 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> > @@ -17,20 +17,21 @@
> > * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> > * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> > * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
> THE USE OR
> > * OTHER DEALINGS IN THE SOFTWARE.
> > *
> > * Authors: Christian König
> > */
> > #ifndef __AMDGPU_RING_H__
> > #define __AMDGPU_RING_H__
> >
> > +#include <drm/amdgpu_drm.h>
> > #include "gpu_scheduler.h"
> >
> > /* max number of rings */
> > #define AMDGPU_MAX_RINGS 16
> > #define AMDGPU_MAX_GFX_RINGS 1
> > #define AMDGPU_MAX_COMPUTE_RINGS 8
> > #define AMDGPU_MAX_VCE_RINGS 3
> >
> > /* some special values for the owner field */
> > #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul)
> > @@ -45,20 +46,21 @@ enum amdgpu_ring_type {
> > AMDGPU_RING_TYPE_SDMA,
> > AMDGPU_RING_TYPE_UVD,
> > AMDGPU_RING_TYPE_VCE,
> > AMDGPU_RING_TYPE_KIQ
> > };
> >
> > struct amdgpu_device;
> > struct amdgpu_ring;
> > struct amdgpu_ib;
> > struct amdgpu_cs_parser;
> > +struct amdgpu_job;
> >
> > /*
> > * Fences.
> > */
> > struct amdgpu_fence_driver {
> > uint64_t gpu_addr;
> > volatile uint32_t *cpu_addr;
> > /* sync_seq is protected by ring emission lock */
> > uint32_t sync_seq;
> > atomic_t last_seq;
> > @@ -130,20 +132,23 @@ struct amdgpu_ring_funcs {
> > void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
> > unsigned (*init_cond_exec)(struct amdgpu_ring *ring);
> > void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned
> offset);
> > /* note usage for clock and power gating */
> > void (*begin_use)(struct amdgpu_ring *ring);
> > void (*end_use)(struct amdgpu_ring *ring);
> > void (*emit_switch_buffer) (struct amdgpu_ring *ring);
> > void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
> > void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
> > void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t
> val);
> > + /* priority functions */
> > + void (*set_priority) (struct amdgpu_ring *ring,
> > + enum amd_sched_priority priority);
> > };
> >
> > struct amdgpu_ring {
> > struct amdgpu_device *adev;
> > const struct amdgpu_ring_funcs *funcs;
> > struct amdgpu_fence_driver fence_drv;
> > struct amd_gpu_scheduler sched;
> > struct list_head lru_list;
> >
> > struct amdgpu_bo *ring_obj;
> > @@ -164,31 +169,41 @@ struct amdgpu_ring {
> > struct amdgpu_bo *mqd_obj;
> > u32 doorbell_index;
> > bool use_doorbell;
> > unsigned wptr_offs;
> > unsigned fence_offs;
> > uint64_t current_ctx;
> > char name[16];
> > unsigned cond_exe_offs;
> > u64 cond_exe_gpu_addr;
> > volatile u32 *cond_exe_cpu_addr;
> > +
> > + atomic_t num_jobs[AMD_SCHED_MAX_PRIORITY];
> > + spinlock_t priority_lock;
> > + /* protected by priority_lock */
> > + int priority;
> > +
> > #if defined(CONFIG_DEBUG_FS)
> > struct dentry *ent;
> > #endif
> > };
> >
> > int amdgpu_ring_is_valid_index(struct amdgpu_device *adev,
> > int hw_ip, int ring);
> > int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
> > void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
> > void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct
> amdgpu_ib *ib);
> > void amdgpu_ring_commit(struct amdgpu_ring *ring);
> > void amdgpu_ring_undo(struct amdgpu_ring *ring);
> > +int amdgpu_ring_elevate_priority(struct amdgpu_ring *ring,
> > + enum amd_sched_priority priority,
> > + struct amdgpu_job *job);
> > +void amdgpu_ring_restore_priority(struct amdgpu_job *job);
> > int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring
> *ring,
> > unsigned ring_size, struct amdgpu_irq_src *irq_src,
> > unsigned irq_type);
> > void amdgpu_ring_fini(struct amdgpu_ring *ring);
> > int amdgpu_ring_lru_get(struct amdgpu_device *adev, int hw_ip,
> > struct amdgpu_ring **ring);
> > void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct
> amdgpu_ring *ring);
> >
> > #endif
> > diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
> b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
> > index 2e458de..5e25674 100644
> > --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
> > +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
> > @@ -149,11 +149,18 @@ void amd_sched_fence_slab_fini(void);
> > struct amd_sched_fence *amd_sched_fence_create(
> > struct amd_sched_entity *s_entity, void *owner);
> > void amd_sched_fence_scheduled(struct amd_sched_fence *fence);
> > void amd_sched_fence_finished(struct amd_sched_fence *fence);
> > int amd_sched_job_init(struct amd_sched_job *job,
> > struct amd_gpu_scheduler *sched,
> > struct amd_sched_entity *entity,
> > void *owner);
> > void amd_sched_hw_job_reset(struct amd_gpu_scheduler *sched);
> > void amd_sched_job_recovery(struct amd_gpu_scheduler *sched);
> > +
> > +static inline enum amd_sched_priority
> > +amd_sched_get_job_priority(struct amd_sched_job *job)
> > +{
> > + return (job->s_entity->rq - job->sched->sched_rq);
> > +}
> > +
> > #endif
>
>
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