From: Huang Rui <[email protected]>
---
amdgpu/amdgpu_gpu_info.c | 48 ++++++++++++++++++++++++++----------------------
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 66c7e0e..cd31e1b 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -175,54 +175,58 @@ drm_private int
amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
AMDGPU_INFO_MMR_SH_INDEX_SHIFT);
r = amdgpu_read_mm_registers(dev, 0x263d, 1, instance, 0,
&dev->info.backend_disable[i]);
if (r)
return r;
/* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
dev->info.backend_disable[i] =
(dev->info.backend_disable[i] >> 16) & 0xff;
- r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
- &dev->info.pa_sc_raster_cfg[i]);
- if (r)
- return r;
-
- if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
- r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance,
0,
- &dev->info.pa_sc_raster_cfg1[i]);
+ if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+ r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance,
0,
+
&dev->info.pa_sc_raster_cfg[i]);
if (r)
return r;
+
+ if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+ r = amdgpu_read_mm_registers(dev, 0xa0d5, 1,
instance, 0,
+
&dev->info.pa_sc_raster_cfg1[i]);
+ if (r)
+ return r;
+ }
}
}
- r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
- dev->info.gb_tile_mode);
+ r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
+ &dev->info.gb_addr_cfg);
if (r)
return r;
- if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
- r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
- dev->info.gb_macro_tile_mode);
+ if (dev->info.family_id < AMDGPU_FAMILY_AI) {
+ r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
+ dev->info.gb_tile_mode);
if (r)
return r;
- }
- r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
- &dev->info.gb_addr_cfg);
- if (r)
- return r;
+ if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+ r = amdgpu_read_mm_registers(dev, 0x2664, 16,
0xffffffff, 0,
+
dev->info.gb_macro_tile_mode);
+ if (r)
+ return r;
+ }
- r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
- &dev->info.mc_arb_ramcfg);
- if (r)
- return r;
+ r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
+ &dev->info.mc_arb_ramcfg);
+ if (r)
+ return r;
+ }
dev->info.cu_active_number = dev->dev_info.cu_active_number;
dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0],
sizeof(dev->info.cu_bitmap));
/* TODO: info->max_quad_shader_pipes is not set */
/* TODO: info->avail_quad_shader_pipes is not set */
/* TODO: info->cache_entries_per_quad_pipe is not set */
return 0;
}
--
2.7.4
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