Re: [PATCH 1/3] drm/amdgpu/vce4: update VCE initialization sequence for SRIOV

[Christian König]

Am 11.04.2017 um 09:30 schrieb Xiangliang Yu:

Update the initialization sequence of VCE to make VCE work.

Signed-off-by: Frank Min <frank....@amd.com>

Acked-by: Christian König <christian.koe...@amd.com> for the whole series.

---
  drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 9 ++-------
  1 file changed, 2 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 8dde83f..d3448d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -280,18 +280,11 @@ static int vce_v4_0_sriov_start(struct amdgpu_device 
*adev)
                init_table += header->vce_table_offset;

ring = &adev->vce.ring[0];

-               INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), 
ring->wptr);
-               INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), 
ring->wptr);
                INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), 
lower_32_bits(ring->gpu_addr));
                INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), 
upper_32_bits(ring->gpu_addr));
                INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_SIZE), 
ring->ring_size / 4);

/* BEGING OF MC_RESUME */

-               INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_CLOCK_GATING_A), ~(1 << 16), 0);
-               INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_UENC_CLOCK_GATING), ~0xFF9FF000, 0x1FF000);
-               INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_UENC_REG_CLOCK_GATING), ~0x3F, 0x3F);
-               INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_CLOCK_GATING_B), 0x1FF);
-
                INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL), 
0x398000);
                INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_LMI_CACHE_CTRL), ~0x1, 0);
                INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_SWAP_CNTL), 
0);
@@ -322,6 +315,8 @@ static int vce_v4_0_sriov_start(struct amdgpu_device *adev)
                                0xffffffff, 
VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK);

/* end of MC_RESUME */

+               INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS),
+                               VCE_STATUS__JOB_BUSY_MASK, 
~VCE_STATUS__JOB_BUSY_MASK);
                INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_VCPU_CNTL),
                                ~0x200001, VCE_VCPU_CNTL__CLK_EN_MASK);
                INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, 
mmVCE_SOFT_RESET),

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