From: Ding Wang <ding.w...@amd.com>
- Set stream signal type to be SST when setting non-tile timing on MST
tiled display.
- Disable MST on sink after disabling MST link.
- Enable MST on sink before enabling MST link.
Change-Id: I809c4fb6b7a83d544c4495230ced16909a7c1bef
Signed-off-by: Ding Wang <ding.w...@amd.com>
Acked-by: Harry Wentland <harry.wentl...@amd.com>
Reviewed-by: Jun Lei <jun....@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +++
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 13 +++++++++++++
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 3 +++
drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 2 ++
4 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index b878fb9697d7..426f7f8187a6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1250,6 +1250,9 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx
*pipe_ctx)
if (link->public.cur_link_settings.lane_count != LANE_COUNT_UNKNOWN)
return DC_OK;
+ /* set the sink to MST mode before enabling the link */
+ dp_enable_mst_on_sink(link, true);
+
return enable_link_dp(pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9f12ba87827a..913b01cd7159 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2453,3 +2453,16 @@ bool dc_link_dp_set_test_pattern(
return true;
}
+
+void dp_enable_mst_on_sink(struct core_link *link, bool enable)
+{
+ unsigned char mstmCntl;
+
+ core_link_read_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
+ if (enable)
+ mstmCntl |= DP_MST_EN;
+ else
+ mstmCntl &= (~DP_MST_EN);
+
+ core_link_write_dpcd(link, DP_MSTM_CTRL, &mstmCntl, 1);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index 3b814592fd70..316df150c1d9 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -129,6 +129,9 @@ void dp_disable_link_phy_mst(struct core_link *link, enum
signal_type signal)
return;
dp_disable_link_phy(link, signal);
+
+ /* set the sink to SST mode after disabling the link */
+ dp_enable_mst_on_sink(link, false);
}
bool dp_set_hw_training_pattern(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index b0cf8e00059c..92c56e6f7588 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -57,4 +57,6 @@ void detect_dp_sink_caps(struct core_link *link);
bool is_dp_active_dongle(const struct core_link *link);
+void dp_enable_mst_on_sink(struct core_link *link, bool enable);
+
#endif /* __DC_LINK_DP_H__ */
--
2.11.0
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