Reviewed-by: Junwei Zhang <[email protected]> Regards, Jerry (Junwei Zhang)
Linux Base Graphics SRDC Software Development _____________________________________ > -----Original Message----- > From: amd-gfx [mailto:[email protected]] On Behalf Of > zhoucm1 > Sent: Friday, April 28, 2017 10:59 > To: [email protected] > Subject: Re: [PATCH] amdgpu: add vm ioctl support > > This is drm patch for dedicated vmid. > Kernel patch has pushed to staging, anyone could have a quick review on this? > Jerry? Guess Christian is in dream at current time. > > Regards, > David Zhou > > On 2017年04月28日 10:38, Chunming Zhou wrote: > > Change-Id: I3c1ea377dad8f6d64a992b071a6ec36a1143e416 > > Signed-off-by: Chunming Zhou <[email protected]> > > --- > > include/drm/amdgpu_drm.h | 22 ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > > > > diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index > > 26d02ba..28cda3a 100644 > > --- a/include/drm/amdgpu_drm.h > > +++ b/include/drm/amdgpu_drm.h > > @@ -47,6 +47,7 @@ > > #define DRM_AMDGPU_GEM_OP 0x10 > > #define DRM_AMDGPU_GEM_USERPTR 0x11 > > #define DRM_AMDGPU_WAIT_FENCES 0x12 > > +#define DRM_AMDGPU_VM 0x13 > > /* hybrid specific ioctls */ > > #define DRM_AMDGPU_SEM 0x5b > > #define DRM_AMDGPU_GEM_DGMA 0x5c > > @@ -66,6 +67,7 @@ > > #define DRM_IOCTL_AMDGPU_GEM_OP > DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct > drm_amdgpu_gem_op) > > #define DRM_IOCTL_AMDGPU_GEM_USERPTR > DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, > struct drm_amdgpu_gem_userptr) > > #define DRM_IOCTL_AMDGPU_WAIT_FENCES > DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, > union drm_amdgpu_wait_fences) > > +#define DRM_IOCTL_AMDGPU_VM > DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union > drm_amdgpu_vm) > > /* hybrid specific ioctls */ > > #define DRM_IOCTL_AMDGPU_GEM_DGMA > DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, > struct drm_amdgpu_gem_dgma) > > #define DRM_IOCTL_AMDGPU_FREESYNC > DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, > struct drm_amdgpu_freesync) > > @@ -201,6 +203,26 @@ union drm_amdgpu_ctx { > > union drm_amdgpu_ctx_out out; > > }; > > > > +/* vm ioctl */ > > +#define AMDGPU_VM_OP_RESERVE_VMID 1 > > +#define AMDGPU_VM_OP_UNRESERVE_VMID 2 > > + > > +struct drm_amdgpu_vm_in { > > + /** AMDGPU_VM_OP_* */ > > + __u32 op; > > + __u32 flags; > > +}; > > + > > +struct drm_amdgpu_vm_out { > > + /** For future use, no flags defined so far */ > > + __u64 flags; > > +}; > > + > > +union drm_amdgpu_vm { > > + struct drm_amdgpu_vm_in in; > > + struct drm_amdgpu_vm_out out; > > +}; > > + > > /* sync file related */ > > #define AMDGPU_SEM_OP_CREATE_SEM 1 > > #define AMDGPU_SEM_OP_WAIT_SEM 2 > > _______________________________________________ > amd-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
