Reviewed-by: Monk Liu <[email protected]>

-----Original Message-----
From: Trigger Huang [mailto:[email protected]] 
Sent: Thursday, May 4, 2017 10:40 AM
To: [email protected]
Cc: Liu, Monk <[email protected]>; Yu, Xiangliang <[email protected]>; 
Huang, Trigger <[email protected]>
Subject: [PATCH] drm/amdgpu: Bypass GMC, UVD and VCE in hw_fini

Some hw finish operations should not be applied in SR-IOV case.
This works as workaround to fix multi-VFs reboot/shutdown issues

Signed-off-by: Trigger Huang <[email protected]>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  6 ++++++  
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |  8 +++++++-  
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 10 ++++++++--
 3 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index dc1e1c1..8f1eb6f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -781,6 +781,12 @@ static int gmc_v9_0_hw_fini(void *handle)  {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       if (amdgpu_sriov_vf(adev)) {
+               /* full access mode, so don't touch any GMC register */
+               DRM_INFO("For SRIOV client, shouldn't do anything.\n");
+               return 0;
+       }
+
        amdgpu_irq_put(adev, &adev->mc.vm_fault, 0);
        gmc_v9_0_gart_disable(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 6e9359d..2dc6127 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -562,7 +562,13 @@ static int uvd_v7_0_hw_fini(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        struct amdgpu_ring *ring = &adev->uvd.ring;
 
-       uvd_v7_0_stop(adev);
+       if (!amdgpu_sriov_vf(adev))
+               uvd_v7_0_stop(adev);
+       else {
+               /* full access mode, so don't touch any UVD register */
+               DRM_INFO("For SRIOV client, shouldn't do anything.\n");
+       }
+
        ring->ready = false;
 
        return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 661f883..6dacada 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -505,8 +505,14 @@ static int vce_v4_0_hw_fini(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        int i;
 
-       /* vce_v4_0_wait_for_idle(handle); */
-       vce_v4_0_stop(adev);
+       if (!amdgpu_sriov_vf(adev)) {
+               /* vce_v4_0_wait_for_idle(handle); */
+               vce_v4_0_stop(adev);
+       } else {
+               /* full access mode, so don't touch any VCE register */
+               DRM_INFO("For SRIOV client, shouldn't do anything.\n");
+       }
+
        for (i = 0; i < adev->vce.num_rings; i++)
                adev->vce.ring[i].ready = false;
 
--
2.7.4

_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Reply via email to